External Memory Disabled warning on new hardware

What are the requested steps to configure the a new board with a DDr2 Memory.

We get an "External Memory Disabled for this Region" warning on the new Hardware"

Are there any Default values loaded for the session (BF607) ????

which XML should we take for adaptions to our Hardware. BF609 EZKit ??? we use nearly the same DDr2 ram.

thanks chris

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  • 0
    •  Analog Employees 
    on Jul 10, 2015 4:13 PM over 5 years ago

    There's no default memory setup done for the BF607. There is an initcode DXE provided that does cgu and memory configuration for the BF609 EZ-Kit, the source for that is in Blackfin/ldr/init_code/BF609_init/BF609_init_v01. The setup done in the IDDE for debugging on the BF609 EZ-Kit is described in System/ArchDef/ADSP-BF609-resets.xml.

    Regards,

    Stuart.

  • Hi, 

    I have the same warning with BF607 and external

    I have edited and tried loading a Custom.xml file, but no success.

    Is there a solution to this?

    Thank,

    Normand

    This XML is attached

    BF607-custom.xml
    <?xml version="1.0" standalone="yes"?>
    
    <custom-cces-proc-xml    xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
        xsi:noNamespaceSchemaLocation="\Analog Devices\CrossCore Embedded Studio 2.9.1\System\ArchDef\ADSP-custom-board.xsd"
    	processor-family="Blackfin"
        file="BF607-custom.xml">
        
    <custom-register-reset-definitions>
      	<!-- Init clocks( CCLK = 500Mhz, SCLK = 250Mhz, SCLK0 = 125Mhz -->
    	<!-- WARNING: Do not change the order of these registers as the -->
    	<!-- WARNING: debugger expects them in a certain order so that  -->
    	<!-- WARNING: it can poll on status bits to make sure the init  -->
    	<!-- WARNING: has completed  									-->
    	<register name="CGU0_DIV" reset-value="0x01024241" core="Common" />
    	<register name="CGU0_CTL" reset-value="0x00001400" core="Common" />
    	
    	<!-- Init DDR0 based on the clock settings above -->
    	<!-- WARNING: Do not change the order of these registers as the -->
    	<!-- WARNING: debugger expects them in a certain order so that  -->
    	<!-- WARNING: it can poll on status bits to make sure the init  -->
    	<!-- WARNING: has completed  									-->
    	<register name="DMC0_CFG" reset-value="0x00000422" core="Common" />
    	<register name="DMC0_TR0" reset-value="0x20F0C424" core="Common" />
    	<register name="DMC0_TR1" reset-value="0x3020079E" core="Common" />
    	<register name="DMC0_TR2" reset-value="0x0032050C" core="Common" />
    	<register name="DMC0_MR" reset-value="0x00000842" core="Common" />
        <register name="DMC0_PHY_CTL3" reset-value="0x050000C4" core="Common" />
    	<register name="DMC0_PHY_CTL1" reset-value="0x00000000" core="Common" />
    	<register name="DMC0_CTL" reset-value="0x00000800" core="Common" />
    	<register name="DMC0_DLLCTL" reset-value="0x0000054B" core="Common" />  
    	
    </custom-register-reset-definitions>
    
    </custom-cces-proc-xml>
    

  • 0
    •  Analog Employees 
    on Apr 10, 2020 1:08 PM 7 months ago in reply to nstjean81

    Hi Normand,
    I've been working on the fix for this warning and unfortunately I've not been able to reproduce the problem, even when using your Custom_resets.xml. Also I've discovered that the bit we're checking to see if DDR initialization is complete should work afterall. So I 'm not sure what the problem is. I compared your file values with those in the CCES 2.9.2 System/ArchDef/ADSP-BF609-resets.xml file and I see that you're setting DMC0_CTL to 0x800 whereas the CCES file uses 0x804. I wonder if you could try using the CCES value to see if that helps?

    When you get the warning, could you check the value of register DMC0_STAT in the register browser DMC0 registers tab. The warning comes out from the emulator when initialization isn't done and that's indicated by bits 1 and 2 of DMC0_STAT. I always see these bit correctly set to 1 but to get the warning they must be 0 for you.

    Would you be able to attach an example DXE that reproduces the problem as perhaps there's something unusual about it that's necessary to reproduce the problem.
    Thanks,
    Stuart.

  • Hi Stuart,

    After modifying Custom_Reset.xml file to have DMC0_CTL to 0x804, same warning appears.

    About DMC0_STAT, right after Application is loaded, at first break line of main(), register indicated 0x000.

    After DDR2_INIT(), DMC0_STAT register is: 0x0040 2007. : IDLE and MEMINITDONE are set, while SRACK is clear.

    I noticed that an instance of the warning message appears for each of these pragma:

    #pragma section("sdram0_bank0")

    #pragma section("sdram0_bank1")

    #pragma section("sdram0_bank2")

    #pragma section("sdram0_bank3")

    When the application uses variables mapped in these section, the warning is displayed.

    About the DXE file, I will prepare an application with no reference to our customer,

    Thanks,

    Normand

  • 0
    •  Analog Employees 
    on Apr 13, 2020 7:28 PM 7 months ago in reply to nstjean81

    Hi Normand,

    That's interesting. It suggests that the setup in DDR2_INIT() works whereas the values loaded by the emulator via the resets xml file doesn't correctly setup the SDRAM. Maybe you could compare the register assignments done in your DDR2_INIT() to the register values defined in Custom_Reset.xml - are there any differences?

    Those #pragma section directives will be used to map variables to SDRAM segments. In a debug session those SDRAM segments get loaded once the emulator has configured the SDRAM using your Custom_Reset.xml. If this isn't working those variables in SDRAM may not have been correctly loaded by the emulator so you may not be able to rely on them having the correct initial values.

    Regards,
    Stuart.

  • Hi Stuart,

    XML matches DMC register values, considering register state one step after exiting DDR_INIT().

    I have attached a DXE that generates the warning output after program is loaded.

    Please rename extention .TXT to .DXE, as .DXE extension caused error during upload...

    DDR_warning_Core0.txt

    Regards,

    Normand

Reply Children
  • 0
    •  Analog Employees 
    on Apr 16, 2020 12:17 PM 7 months ago in reply to nstjean81

    Hi Normand,

    Unfortunately the problem didn't reproduce for me using the BF609 EZ-KIT with your example DXE. It seems there is some problem using the reset XML file but I don't know what that is at the moment.

    Could you try creating what we call a preload using your DDR2_INIT() source. It's basically a simple DXE that does the initialization that would normally be done in your loader stream initcode that gets used in the debug session. The essential thing for the preload is that it shouldn't use SDRAM. Your preload source might just be:

    void DDR2_INIT() {
    ...snip...
    }

    int main() {
      DDR2_INIT();
      return 0;
    }

    Your debug session needs to be changed to first load the built preload dxe followed by the application with no reset between the two dxe loads. Here's a screen shot of the debug session setup I tried. The add button is used to add the additional new preload DXE.




    The preload used in this way will setup the DDR2 for the application load replacing the need to the resets XML.

    Regards,
    Stuart.

  • hi Stuart,

    You suggestion was correct. No more "warning - external memory ..." when using preload.

    Thank you for you help!

    Normand