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Exception Handler in CCES

		
	
				

			

									
					    pfeifferc
					
							

            
            			
				
									
											
			
			
				
			
			
			    	
			                    
                
				                on Mar 30, 2016 
				
			
			
		

		
		                    	    

        	    
Thread Summary

                The user inquires about handling exceptions in SSL2.0, specifically ADI_EXC_INSTR_CPLB_MISS, after successfully setting up a handler for ADI_EXC_DATA_MISALIGNED. The solution involves ensuring valid CPLB entries for accessed memory regions and dynamically managing CPLBs if all entries are used. The user's code snippet is deemed correct, but no C source for exception handlers is available, only ASM examples in the Blackfin Programming Reference Manual.
                        	    

                
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The documentation video&slides concerning the migration from SSL1.0 to SSL2.0 mentions

 
that exception handlers for HW_errors and exception could eliminated in SSL

 
But I get Exceptions(Data misalignments) in my code and want also handle other exceptions.

 
What is the correct way to handle this in SSL2.0

 
I use

 
adi_int_InstallHandler (ADI_EXC_DATA_MISALIGNED, ExceptionHandler,NULL,true);

 
to get the exception for DATA_misaligments - this works.

 
but how can I setup e.g. an ADI_EXC_INSTR_CPLB_MISS exception

 
to the same interrupt-handler ??

 
my handler is defined via

 
int ExceptionHandler(uint32_t iid, void* handlerArg)

 
{      int illegalMemAccess;

 
     unsigned short mask;

 
 mask=sysreg_read(reg_SEQSTAT) & EX_BITS;

 
if(0x24==mask) illegalMemAcces=1;

 
while(1) {}

 
}

			

			
									
		                             
                        

    

                                            
                 cces
                
                                                    
                 exceptions
                
                                                    
                 ssl2.0
                
                                                    
                 interrupts
                
                                
            

    
    
		


				
				        
        		

			
						
									
												
			
			
                        
                                    
                        
                        
                        
            
			            
						
						
			
			
			
			
		


        
        
        
    
					

			





















	

	

					



			








	
	
	
	



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    •  Analog Employees  
    
            
						
                            
            
            				
            
                on Apr 8, 2016 12:05 PM
            
            
						
			            		
    
		
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    Hi ,
    
 
    If you are using CPLBs, it is necessary that you have a valid CPLB entry defined for every memory region that you access (you need not enable cache though). In case you access a memory that does not have a valid CPLB entry, you will get this exception.
    
 
    The Blackfin Programming Refernce Manual has more details on this error. The Table titled "Events That Cause Exceptions" in the chapter "Program Sequencer" gives details on the different exceptions. The type of exception caused, and the reason why it is caused can be identified by viewing the EXCAUSE field in the SEQSTAT register (Register -> Core -> Status -> Sequencer Status).
    
 
      
    
 
    From the table of EXCAUSE values, you can identify if you have got an instruction CPLB miss or a data CPLB miss. If it is an instruction CPLB miss, you can find the instruction that caused it to happen by looking at the RETX register. (Register -> Core -> Sequencer -> RETX). Also, the faulting address can be found from the I/DCPLB_STATUS registers. You can now add a CPLB entry for the region of memory that covers this faulting address.
    
 
    If you have used up all 16 CPLB entries, then you will have to dynamically manage the CPLBs to service this exception, by having a CPLB replacement policy in place. The exception handler uses the faulting address to index into the Page DescriptorTable structure to find the correct CPLB descriptor data to load into one of the on-chip CPLB register pairs. If all on-chip registers contain valid CPLB entries, the handler selects one of the descriptors to be replaced, and the new descriptor information is loaded. Before loading new descriptor data into any CPLBs, the corresponding group of sixteen CPLBs must be disabled using:
    
 
    •The Enable DCPLB (ENDCPLB) bit in the DMEM_CONTROL register for data descriptors, or
    
 
    • The Enable ICPLB (ENICPLB) bit in the IMEM_CONTROL register for instruction descriptors
    
 
    After the new CPLB descriptor is loaded, the exception handler returns, and the faulting memory operation is restarted. this operation should now find a valid CPLB descriptor for the requested address, and it should proceed normally.
    
 
    More details on this are given under the section "CPLB Management" of the Programming Reference Manual.
    
 
    Best Regards,
    
 
    Kader
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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    •  Analog Employees  
    
            
						
                            
            
            				
            
                on Apr 8, 2016 12:05 PM
            
            
						
			            		
    
		
										0
					
	
    

		
		
    
		
    
                                
                                                            
    
					
    Hi ,
    
 
    If you are using CPLBs, it is necessary that you have a valid CPLB entry defined for every memory region that you access (you need not enable cache though). In case you access a memory that does not have a valid CPLB entry, you will get this exception.
    
 
    The Blackfin Programming Refernce Manual has more details on this error. The Table titled "Events That Cause Exceptions" in the chapter "Program Sequencer" gives details on the different exceptions. The type of exception caused, and the reason why it is caused can be identified by viewing the EXCAUSE field in the SEQSTAT register (Register -> Core -> Status -> Sequencer Status).
    
 
      
    
 
    From the table of EXCAUSE values, you can identify if you have got an instruction CPLB miss or a data CPLB miss. If it is an instruction CPLB miss, you can find the instruction that caused it to happen by looking at the RETX register. (Register -> Core -> Sequencer -> RETX). Also, the faulting address can be found from the I/DCPLB_STATUS registers. You can now add a CPLB entry for the region of memory that covers this faulting address.
    
 
    If you have used up all 16 CPLB entries, then you will have to dynamically manage the CPLBs to service this exception, by having a CPLB replacement policy in place. The exception handler uses the faulting address to index into the Page DescriptorTable structure to find the correct CPLB descriptor data to load into one of the on-chip CPLB register pairs. If all on-chip registers contain valid CPLB entries, the handler selects one of the descriptors to be replaced, and the new descriptor information is loaded. Before loading new descriptor data into any CPLBs, the corresponding group of sixteen CPLBs must be disabled using:
    
 
    •The Enable DCPLB (ENDCPLB) bit in the DMEM_CONTROL register for data descriptors, or
    
 
    • The Enable ICPLB (ENICPLB) bit in the IMEM_CONTROL register for instruction descriptors
    
 
    After the new CPLB descriptor is loaded, the exception handler returns, and the faulting memory operation is restarted. this operation should now find a valid CPLB descriptor for the requested address, and it should proceed normally.
    
 
    More details on this are given under the section "CPLB Management" of the Programming Reference Manual.
    
 
    Best Regards,
    
 
    Kader
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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