Post Go back to editing

Using SDRAM

Thread Summary

The user encountered an error when trying to load a section to SDRAM for Core 1 of the SHARC SC594 on the EZ-KIT SC594W. The issue was resolved by using a second new board, suggesting a hardware-specific problem. Key steps included confirming the project builds and loads without SDRAM, checking the LDF file, and ensuring the correct debug configuration was used. The problem occurred on both CCES 2.10.1 and 2.11, and on multiple PCs.
AI Generated Content
Category: Software
Product Number: ADSP-SC594

Hello,

I want to use SDRAM for core 1 of the SHARC by selecting that

for the example AD_Talkthrough_TDM_SC594_SHARC_Core1.

I have use C:\Analog Devices\CrossCore Embedded Studio 2.10.1\SHARC\ldr\ezkitSC594W_preload_core0 for core0.

However, I have this error:

error loading section dxe_sdram_cpp_ctors_nw to target at core 1

Then:

[TpsdkServer] Failed to load file: AD_Talkthrough_TDM_SC594_SHARC_Core1.dxe [Error: Failed to connect to target., Code=0x80047344]

Could you please help me?

Thread Notes

Parents
  • Hi,

    To assist and understand your system better, could you please reply for the below questions:
    1.Could you please confirm that the project is build and loads fine without using SDRAM.
    2.Are you using Custom board or EZ-KIT. If it is custom board, could you please share us the DDR part number.

    Regards,
    Nandini C

  • Hi,

    1.Could you please confirm that the project is build and loads fine without using SDRAM. -> Yes, it's fine without using SDRAM
    2.Are you using Custom board or EZ-KIT. If it is custom board, could you please share us the DDR part number -> we are using EZ-Kit, SOM (EV-SC594-SOM RevC)

    Thanks,

  • Hi,

    We are unable to simulate the issue here.

    Could you please confirm whether you have modified the LDF file to utilize the SDRAM section? If yes, please share the updated LDF file along with the changes made in the project’s source files.

    This information will help us proceed further.

    Regards,
    Santhakumari.V

  • I add this line of code: section("seg_sdram") float FIRsCoeff[4* (4 +1)* 8 * 256 * sizeof(float)]; in the Audio_Talkthrough_TDM.c of Core1. change the cache to 128 for core1, add 

    I do not modify the app.ldf

  • Hi,

    We were unable to reproduce the issue with the same details you have provided.

    We are tried with EV-SC594-SOM Rev C and EV-SOMCRR-EZKIT Rev A on CCES 2.10.1.

    Could you please try creating a new workspace and perform a clean build of your project and trying debug?

    Also, confirm whether the SDRAM mapping you configured is correctly reflected in the "map.xml" file.

    If the issue persists, please share a short video clip demonstrating the problem with all the steps you followed.

    Regards,
    Santhakumari.V

Reply
  • Hi,

    We were unable to reproduce the issue with the same details you have provided.

    We are tried with EV-SC594-SOM Rev C and EV-SOMCRR-EZKIT Rev A on CCES 2.10.1.

    Could you please try creating a new workspace and perform a clean build of your project and trying debug?

    Also, confirm whether the SDRAM mapping you configured is correctly reflected in the "map.xml" file.

    If the issue persists, please share a short video clip demonstrating the problem with all the steps you followed.

    Regards,
    Santhakumari.V

Children
  • ADI_SDRAM.zip

    Hi,

    I apologize for the delayed response. Here are the videos to show our problem.

    Regards,

    Van Khanh MAI

  • Hi,

    From the video, we understand that you have enabled the "Load symbols only" option while debugging for the ARM core applications. Refer the screenshot attached.

    Load symbols only-> can be used when the boot process fails, very little information can be gained by watching the chip from outside.

    So, could you please delete the existing session configuration, create a new session, and try once.

    We have seen this issue before when the preload code failed to load due to some incorrect configuration. Please let us know whether you have modified the preload code.

    Also, please let us know which carrier board(SOMCRR-KIT or SOMCRR-EZLITE) and Rev. that you are using with SC594-SOM.

    Regards,
    Santhakumari.V

  • Hi, 

    I tried it many times, and I got the same result. Our carrier board is EV-SOMCRR-EZKIT with Rev C.

    Regards,

    Van Khanh MAI

  • Hi,

    We were able to reproduce the issue on our side when we enabled the "Load symbols only" option in the debug configuration for the ARM core.

    From the video you shared, we noticed that the debug session starts with the message "Loading symbols …" for the ARM core. We suspect this configuration will be the cause of the issue.

    Please refer to the attached videos showing the working and non-working scenarios.

    Could you please try once again with the default debug configuration (as shown in the working video) and let us know the results.

    As you have also contacted our private support, please continue the discussion there to avoid duplications.

    Thanks!

    CS-537647-X9W7Q8.zip


    Regards,
    Santhakumari.V

  • Hi, 

    I tried your debug configuration, and it still doesn't work for us. The connection is EZ-KIT lite.

    Thanks!

    Regards,

    Van Khanh MAI

  • Here is the video for this configuration.

  • Hi,

    Unfortunately, We are unable to reproduce the issue using the EZ-KIT debug agent session.

    To help us isolate the problem, could you please provide clear answers to each of the following points:

    1. Create a new workspace, perform a clean build of your project, and attempt to debug again.
    2. Confirm whether this issue occurs only with your specific project, or if changing the SDRAM configuration in any other simple project also triggers the same problem.
         • If the issue is limited to your specific project, please share the complete project along with the workspace folder.
    3. If possible, test with any newer version of CCES (beyond CCES 2.10.1).
    4. Try reproducing the issue on a different PC and share the results.
    5. Let us know if you have used this board before, or if this is your first time working with it.
    6. If feasible, reinstall CCES and test with a fresh installation, then let us know the outcome.

    Regards,
    Santhakumari.V

  • Hi, 

    1. Create a new workspace, perform a clean build of your project, and attempt to debug again -> yes, the same issue
    2. Confirm whether this issue occurs only with your specific project, or if changing the SDRAM configuration in any other simple project also triggers the same problem -> all projects have the same issue with adjusting the SDRAM configuration
         • If the issue is limited to your specific project, please share the complete project along with the workspace folder.
    3. If possible, test with any newer version of CCES (beyond CCES 2.10.1). -> Yes on CCES2.11
    4. Try reproducing the issue on a different PC and share the results. -> Yes, we tried with another PC, same issue
    5. Let us know if you have used this board before, or if this is your first time working with it -> we have used it without sdram configuration
    6. If feasible, reinstall CCES and test with a fresh installation, then let us know the outcome -> same issue

    Thanks,

  • Hi,

    Based on the information provided, we understand that the issue does not appear to be related to the software.

    To further isolate the cause, could you confirm whether you have any other boards to check this scenario.

    If so, please replicate this scenario on another board and share the results with us. This will help us determine the next steps and proceed with a further investigation.

    Thanks for understanding.

    Regards,
    Santhakumari.V

  • Hi, 

    As you have recommended, we bought a new board and tested on it, but we have the same results.

    Could you please help us?

    Regards,

    Van Khanh

Before You Switch


Switching languages will make ADI Explorer unavailable. Resume your session by switching back to English and reopening ADI Explorer.