Cycle Count Difference in SHARC-FX When Function Definition and Call Are in Separate Files

Question

Dear Team, 
 I am working in 21834 processor (SHARC-FX), in simulation I am observing a difference in cycle counts when running the same function in two scenarios: 
 
 Are there any specific compiler settings, optimization behaviors, or inlining considerations in SHARC-FX that could cause such differences? 
 Please share the root cause of this behavior. 
 
 Thanks, and regards 
 Franky45

Santhakumari · Accepted Answer

Hi Frank, 
 Apologies for the delay in response. 
 SHARC+ core was designed internally within ADI while SHARC-FX is developed by Cadence, these cores are completely different architectures and as such the expected behaviour on similar operations may differ, Details on the SHARC-FX core can be obtained from your cces directory ${CCES_HOME}/Xtensa/Docs/xtensa_nx_data_book.pdf. We are following up with Cadence regarding the MMR write behaviour. The higher cycle counts observed on SHARC-FX when the function call and function definition are placed in different files, compared to when both are in the same file is due to the compiler and linker optimizations. There is a command line switch to be added to the Compiler and Linker '-flto' with performs Link-Time-Optimisation for cross-translation-unit-inlining. This resolved the biggest difference in cycle counts as marking the routine is &ldquo;inline&rdquo; doesn&rsquo;t work because the compiler can&rsquo;t see it in both places. With '-flto' added, both the compiler and linker will remember the routine and can inline the functions. 
 Hope this helps. 
 Best Regards, Santhakumari.V)

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Cycle Count Difference in SHARC-FX When Function Definition and Call Are in Separate Files

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