Hello,
I am working with the following hardware, where the cable connects LinkPort_0 (Tx) to LinkPort_1 (Rx) of SOMCRR
In EV-SOMCRR-EZLITE the switches S1 and S2 are set in Local_JTAG mode (Table 3-5 of the manual, S1: ON OFF ON OFF ON OFF S2: ON OFF ON OFF OFF OFF) to not interfer with LinkPort at all.
On the software side I work with CCES 3.0.2, I have only initialized a few GPIO for debug purposes (PA_10, PA_11, PA_12), SOM LEDs through soft switches and SOM USB-UART logs through UART0. Then I have written a very simple loopback code for testing LinkPort communication, setting:
- max possible speed with adi_linkport_ConfigClock( linkPortTxHandle, 0 )
- 8 bit DDR data transfer (ADI_LINKPORT_DDR_8BIT_TRANSFER_MODE)
- Tx and Rx data buffers located in section(".L1.data") aligned to 64 bit addresses - also tested 32 bit alignment
- Tx working in ENUM_DMA_CFG_PERIPH_INT ISR mode, Rx working in ENUM_DMA_CFG_XCNT_INT ISR mode
- ADSP-SC835 internal PullDown resistors for all LinkPort_0 and LinkPort_1 data lines
- *pREG_PADS0_PORTB_PDE |= 0b1111111110000000;
- *pREG_PADS0_PORTC_PDE |= 0b1111111;
As I test different clock frequencies for Tx linkport with adi_linkport_ConfigClock( linkPortTxHandle, DIV ), signal starts to deteriorate as follows:
- DIV = 3, Fclk = 20.8 MHz: communication working perfectly
- DIV = 2, Fclk = 31.3 MHz: very eventually some data gets corrupted in bit number 3 (LinkPort_x D3)
- DIV = 1, Fclk = 62.5 MHz: more frequent failures in bit number 3
- DIV = 0, Fclk = 125.0 MHz: almost 100% of the data gets corrupted in bit number 3
This behaviour is the same whether I run a debug session with ICE-1000 from CCES, or code is loaded from SOM flash memory with ICE-1000 disconnected from SOM.
Is it possible that I am missing to configure something on the SOMCRR side that could be interfering with that specific data line? Shouldn't the system be able to operate without any data loss given we are using all the recomended hardware?
Thanks
