Not reaching 8 MACs per cycle in SHARC-FX core processing

Hi Leopoldo,

The main reasons why the code below does not get 1 PDX_MULA_MXF32 per cycle is because:

1) There is inner loop overhead to set up and shut down the loop with some stalls
2) There is a reduction of the unrolled accumulators to a single output vector, with more stalls
3) A little outer loop overhead

In the big picture, the issue is that the overhead outside the loop is significant compared to what happens inside the loop.

Here's what the code looks like when all in-lined:
// firInlineRun
START_CYCLE_COUNT (var);
for (int i=0; i<20; i++) {
  // macTest
  vectorSum = 0;
  for (int i=0; i<72; i++) {
    PDX_MULA_MXF32(vectorSum, inVectors[inChannel][i], coeffVectors[inChannel][i]);
  }
  outVectors[outChannel][0] = vectorSum;
}
STOP_CYCLE_COUNT (cyc, var);

The cycle counter reports 2031 cycles to do 20*72=1440 MULAs, or 101 cycles per macTest. The inner loop really does take 72 cycles spinning on the MULAs, so there are 29 of overhead.

The overall breakdown of one pass looks like:
| Cyc | Phase |
|-----|-----------------|
|   8 | loop prologue |
|  72 | loop |
|   8 | loop epilogue |
|   8 | unrolled accumulator reduction |
|   4 | outer loop overhead |
| 100 | total |

14 are stalls. There is an extra cycle for an initial Icache miss.

There are tools outside of CCES that can be used to profile this down to the instruction level, but let me describe those separately.

Hi jlredford , any chance you could please elaborate on the tools that can be used to profile the code/instructions?
Many thanks, 
Simon

Hi jlredford , any chance you could please elaborate on the tools that can be used to profile the code/instructions?
Many thanks, 
Simon