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response time: ISR_CORE vs ISR_SEC

Category: Hardware
Product Number: ADSP21569

Hi.

When I tested modified interrupt dispatcher I compared response time for core interrupt service vs SEC interrupt service.

The timecore interrupt service with high priority (ISR_TMZHI) looks:

___int_CORE_ESDSF_TMZHI:        // 0x2c  Timer=0 (high priority option)
bit set irptl BITM_REGF_IRPTL_SFT1I;
rti (db);
     bit tgl flags BITM_REGF_FLAGS_FLG0;
    nop;
___int_CORE_ESDSF_TMZHI.end:

The core software 0 interrupt service looks:

___int_CORE_ESDSF_SFT1I:	// 0x74  User software interrupt 1
#if	1
	bit set irptl BITM_REGF_IRPTL_SFT0I;
	rti (db);
		bit tgl flags BITM_REGF_FLAGS_FLG1;
		nop;
___int_CORE_ESDSF_SFT1I.end:

The SEC interrupt service looks:

___int_SEC:					// 0x3c  System event controller interrupt
	dm(__DispatcherSaveI7)		= i7;
	jump	__dispatcher_SEC_mod (db);
		dm(__DispatcherSaveB7)	= b7;
		bit tgl flags BITM_REGF_FLAGS_FLG1;
	___int_SEC_SF.end:

The code of __dispatcher_SEC_mod is similar the code of __dispatcher_SEC which take into account changing SEC interrupt vector.

The response time is measured from toggle FLG0 in ISR_TMZHI to toggle FLG1 in ISR_SFT1I or ISR_SEC.

If ISR_SFT1I is enabled than ISR_SEC is disable and otherwise.

So oscilloscope show that response time for ISR_CORE take about 23 processor cycles.

So oscilloscope show that response time for ISR_SEC take about 55 processor cycles.

I didn't find information that SEC is delayed interrupt.

Can you explain it and take to direct manuals when it describe.

Best regards.



fixing error
[edited by: daim at 2:17 PM (GMT -4) on 11 Jul 2024]

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