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ADSP-SC573 with AD73360 via SPORT

Hi everyone,

I'm trying to interface two AD73360 in cascade from ADSP-SC573 SPORT0 but without success.

The connection is the one proposed in the ADC's manual:

It's a Frame Sync Loop-Back.

From DSP's perspective, we have these connections:

DAI0_PPB01 Output DT
DAI0_PPB02 Input SCLK
DAI0_PPB03 Input DR
DAI0_PPB04 Input TFS/RFS

I configured the SRU via the SRU() macro and not via the plugin as such:

void SRU_Config(void)
{
	// DAI0_PB02 provides clock for SPORTA (externally supplied CLK)
	SRU(DAI0_PB02_O, 	SPT0_ACLK_I);
	SRU(LOW,			DAI0_PBEN02_I);
	SRU(LOW, 			DAI0_PB02_I);

	// DAI0_PB02 provides clock for SPORTB (externally supplied CLK)
	SRU(DAI0_PB02_O, 	SPT0_BCLK_I);
	SRU(LOW, 			DAI0_PBEN02_I);	// dup
	SRU(LOW, 			DAI0_PB02_I);	// dup

	// DAI0_PB04 provides frame sync for SPORTA (externally supplied FS)
	SRU(DAI0_PB04_O, 	SPT0_AFS_I);
	SRU(LOW, 			DAI0_PBEN04_I);
	SRU(LOW, 			DAI0_PB04_I);

	// DAI0_PB04 provides frame sync for SPORTB (externally supplied FS)
	SRU(DAI0_PB04_O, 	SPT0_BFS_I);
	SRU(LOW, 			DAI0_PBEN04_I);	// dup
	SRU(LOW, 			DAI0_PB04_I);	// dup

	// DAI0_PB03 is an input to SPORTB
	SRU(DAI0_PB03_O,	SPT0_BD0_I);
	SRU(LOW, 			DAI0_PBEN03_I);
	SRU(LOW, 			DAI0_PB03_I);

	// SPT0_AD0 outputs to DAI0_PB01
	SRU(SPT0_AD0_O,	DAI0_PB01_I);
	SRU(SPT0_AD0_PBEN_O, DAI0_PBEN01_I);
}

The ARM core configures the clock generator that feeds the ADCs.

The SHARC core 0 configures the SRU and is responsible for "speaking" with the ADCs:

  1. Configures SRU
  2. Resets ADCs
  3. Enables ADC SPORT by setting SE
  4. Configures DSP's SPORT
  5. Puts ADCs out of reset
  6. Transmits the control words
  7. ...

After step 6, I cannot see any control word be transmitted in my waveforms. I can only verify the default state of the ADCs as described in the manual, eg. the SCLK period is the default one, Frame Syncs appear after 2070 cycles of the master clock, etc.

Do you think the SRU is configured correctly?

EDIT:

Please find attached the Core1 CCES project that does most of the things. It uses the my attempt to configure SRU via the plugin. 

adc.zip



Added example code.
[edited by: gon1332 at 3:58 PM (GMT -4) on 15 Apr 2022]
  • Hi,

    We have reviewed the SRU file.

    From this we understand that you are providing clock via DAI0_PB02_O to SPORT0A and SPORT0B

    Framesync is given via DAI0_PB04_O to SPORT0A and SPORT0B

    But the following line, SRU(SPT0_AD0_PBEN_O, DAI0_PBEN01_I); we do not have PBEN option for SPORTs datalines.Pin buffer enable option is only applicable for DAI pin buffers.

    You can also refer macro kind of SRU configuration in the following BSP example path. You can use this as a reference for your project.

    C:\Analog Devices\EV-2156x_EZ-KIT-Rel1.0.1\EV-2156x_EZ-KIT\Examples\drivers\adc\Audio_Passthrough_I2S

    Also I am attaching a simple loopback code with macro SRU configuration for your reference

    We request you to refer SC573 audio example project from the below path

    C:\Analog Devices\ADSP-SC5xx_EZ-KIT_Lite-Rel2.0.2\ADSP-SC5xx_EZ-KIT\Examples\drivers\adc\adau1979\adc_dac_playback

    Please try and let us know how you are getting on.

    Best Regards,
    Santhakumari.K

    5504.SC573_Callback.zip

  • Hi Santhakumari,

    Thanks for the reply.

    By following your advice I've changed the SRU configuration as such:

    void SRU_Config(void)
    {
    	// DAI0_PB02 provides clock for SPORTA & SPORTB (externally supplied CLK)
    	SRU(LOW,			DAI0_PBEN02_I);
    	SRU(LOW, 			DAI0_PB02_I);
    	SRU(DAI0_PB02_O, 	SPT0_ACLK_I);
    	SRU(DAI0_PB02_O, 	SPT0_BCLK_I);
    
    	// DAI0_PB04 provides frame sync for SPORTA & SPORTB (externally supplied FS)
    	SRU(LOW, 			DAI0_PBEN04_I);
    	SRU(LOW, 			DAI0_PB04_I);
    	SRU(DAI0_PB04_O, 	SPT0_AFS_I);
    	SRU(DAI0_PB04_O, 	SPT0_BFS_I);
    
    	// SPORTA outputs data to DAI0_PB01
    	SRU(HIGH, 	 	 	DAI0_PBEN01_I);
    	SRU(SPT0_AD0_O, 	DAI0_PB01_I);
    
    	// DAI0_PB03 is a data input to SPORTB
    	SRU(LOW, 			DAI0_PBEN03_I);
    	SRU(LOW, 			DAI0_PB03_I);
    	SRU(DAI0_PB03_O,	SPT0_BD0_I);
    }

    Problem persists.

    I verified with an o-scope that after reset, SCLK and Fs frequencies are as the ADC manuals.

    When I try to send the first control word to set the dividers for the ADCs, it doesn't get sent (verified in the o-scope). However, the Tx callback reports that the output has been processed.

    The initialization of the SPORT that interfaces with the ADCs can be seen in the adc_ddk_Core1/src/adc.c path of the project that I'm attaching.

    I have tried both Tx interrupt mode and Tx in DMA mode.

    I've seen the ADC-DAC playback example but I don't know what I'm missing here.

    Looking forward to your reply.

    5040.adc.zip

  • Hi,

    Apologies for the delay in response.

    Can you please share the design schematics of AD73360 with ADSP-SC573 processor.

    Best Regards,
    Santhakumari.K

  • Hi,

    We understood that after adding proper SPU IDs in your application, the DMA transaction issue got resolved in your side.

    Best Regards,
    Santhakumari.K