Hi everyone,
I'm trying to interface two AD73360 in cascade from ADSP-SC573 SPORT0 but without success.
The connection is the one proposed in the ADC's manual:
It's a Frame Sync Loop-Back.
From DSP's perspective, we have these connections:
| DAI0_PPB01 | Output | DT |
| DAI0_PPB02 | Input | SCLK |
| DAI0_PPB03 | Input | DR |
| DAI0_PPB04 | Input | TFS/RFS |
I configured the SRU via the SRU() macro and not via the plugin as such:
void SRU_Config(void)
{
// DAI0_PB02 provides clock for SPORTA (externally supplied CLK)
SRU(DAI0_PB02_O, SPT0_ACLK_I);
SRU(LOW, DAI0_PBEN02_I);
SRU(LOW, DAI0_PB02_I);
// DAI0_PB02 provides clock for SPORTB (externally supplied CLK)
SRU(DAI0_PB02_O, SPT0_BCLK_I);
SRU(LOW, DAI0_PBEN02_I); // dup
SRU(LOW, DAI0_PB02_I); // dup
// DAI0_PB04 provides frame sync for SPORTA (externally supplied FS)
SRU(DAI0_PB04_O, SPT0_AFS_I);
SRU(LOW, DAI0_PBEN04_I);
SRU(LOW, DAI0_PB04_I);
// DAI0_PB04 provides frame sync for SPORTB (externally supplied FS)
SRU(DAI0_PB04_O, SPT0_BFS_I);
SRU(LOW, DAI0_PBEN04_I); // dup
SRU(LOW, DAI0_PB04_I); // dup
// DAI0_PB03 is an input to SPORTB
SRU(DAI0_PB03_O, SPT0_BD0_I);
SRU(LOW, DAI0_PBEN03_I);
SRU(LOW, DAI0_PB03_I);
// SPT0_AD0 outputs to DAI0_PB01
SRU(SPT0_AD0_O, DAI0_PB01_I);
SRU(SPT0_AD0_PBEN_O, DAI0_PBEN01_I);
}
The ARM core configures the clock generator that feeds the ADCs.
The SHARC core 0 configures the SRU and is responsible for "speaking" with the ADCs:
- Configures SRU
- Resets ADCs
- Enables ADC SPORT by setting SE
- Configures DSP's SPORT
- Puts ADCs out of reset
- Transmits the control words
- ...
After step 6, I cannot see any control word be transmitted in my waveforms. I can only verify the default state of the ADCs as described in the manual, eg. the SCLK period is the default one, Frame Syncs appear after 2070 cycles of the master clock, etc.
Do you think the SRU is configured correctly?
EDIT:
Please find attached the Core1 CCES project that does most of the things. It uses the my attempt to configure SRU via the plugin.
Added example code.
[edited by: gon1332 at 3:58 PM (GMT -4) on 15 Apr 2022]
