Error while running the InterleavedFFTPipelined example

Hi,

We are able to run the InterleavedFFTPipelined example here with CCES 2.10.0 on ADSP-SC589 EZKIT successfully with out any issues. Please refer the attached screenshot "fft_example.png".

Therefore, could you please try deleting the existing debug configurations and then delete the project, close the IDE. Now then restart the CCES from first (create new workspace)and import a project as fresh and launch a new debug configurations and see if the issue still exists.

Also, Could you please let us know whether you have set any function breakpoints using "breakpoints view" and try connect your session. If so, this is a known issue.

If so, Please remove the breakpoint and try to add a breakpoint at a function in CCES, using the below procedure.

1. Open the project in CCES IDE and build the project.
2. In the C/C++ perspective, in the outline view, right-click the function you want to add breakpoint (e.g. add_ver) and select “Toggle Breakpoint”, a red dot will add behind the function in the editor. (refer to screenshot breakpoint.jpg) 3. Launch a debug configuration with CrossCore Debugger and run the project. You can see the breakpoint hitting on the function add_ver as expected. (refer to screenshot debug.jpg)

If this issue not due to breakpoints, Please let us know the CCES version and operating system that you are using. Also, Could please try in different machines and let us know how you gets on.

The below FAQ CrossCore® Embedded Studio – Getting Started would give you better insight,
ez.analog.com/.../crosscore-embedded-studio-getting-started

We have a number of CCES introductory videos on our Analog Devices Video Channel. These videos are also indexed on the CrossCore Embedded Studio product page which is linked below.
www.analog.com/.../adswt-cces.html

Regards,
Santhakumari.K

Ezone_557421.zip

Dear Santhakumai.K,

Thanks a lot! I was able to get the same results.

Can you explain further how can I plot the graph of the generated FFT?

Also, can I use only one core for example, Core1 and not Core0 and Core2? I am mainly interested in hardware based FFT and Core1 is based on SHARC which has that as an inherit ability.

Best regards,

Amrit Zoad

Hi,

CCES includes Plot View window to display a plot, a visualization of values obtained from processor memory.

To access the Plot view from the Debug perspective, choose Window > Show View > Other > Debug > Plot and click OK.

Also to view Plot window, please follow the below steps:
Open the Plot view via “Window: Show View: Plot”.
To access the PlotConfiguration dialog box, click Configure Plot from the toolbar of the Plot view.
In Type, select a plot type and Click New.
In Memory, select a memorytype;
In Address, Click ...(Browse), the Symbol Selection dialog box appears. Choose a symbol(eg: fwd_out/inv_out) and click OK.
The symbol appears in Address of the Edit Data Set dialog box.
In Data type, select the data type of the address. By default it shows "Signed integer".
Change the datatype format as per your requirement, now the changed data set appears in the Plot view.

We recommend you to refer the below CCES help path for more details on plotting:

CrossCore® Embedded Studio 2.10.1 > Integrated Development Environment > Debugging Executable Files > Visualizing Processor Memory with Plots > About Plotting

CrossCore® Embedded Studio 2.10.1 > Integrated Development Environment > Debugging Executable Files > Visualizing Processor Memory with Plots > Plot View

Also when the processor starts execution, the SHARC+ cores are held in IDLE until enabled by the application running on the ARM core. This means:
*If the application running on core 0 does not explicitly enable the other cores, the SHARC+ cores will not run their applications.
*When the application is loaded into the processor using the debugger and run to the start of main() on core 0, the other cores will still be in IDLE.
*The run-time libraries include the adi_core_enable() function to release other cores from IDLE.

Therefore, the below code generated by CCES "adi_Core_Enable functions in arm core(core0)" is needed to bring the SHARC cores out of reset. However, you can have your application in sharc core alone.

adi_core_enable(ADI_CORE_SHARC0);
adi_core_enable(ADI_CORE_SHARC1);

Regards,
Santhakumari.K