Question: An instruction CPLB miss occurs after 125 PPI interrupts(or uart interrupts). is there a maximum amount of PPI (or other) interrupts that can occur during a program? do we have to periodically clear some registers?
Here is a detailed description of the problem:
we are using PPI in Rx mode only to receive data. PPI is configured in interrupt callback mode:
1. a buffer is assigned to PPI.
2. when the buffer gets filled, it invokes the callback function.
3. callback function determines the next available buffer to use, assigns it to the PPI, re-enables PPI, and then exits to main program.
4. The error "An instruction CPLB miss" happens PRECISELY at the 125th occurrance of the PPI callback function. (error message below)
What we tried:
1. we used dummy codes in PPI callback function and verified that the error is not caused by memory jams.
2. after disabling other peripherals, we've confirmed that the error is not related to rest of our codes.
3. also this error not only applies to PPI interrupt. If PPI is disabled, the same problem also happens to uart at approximately 100+ interrupts.
Here is a brief description of our custome board design, it features:
- a BF527 DSP chip;
- 64MB of external DRAM chip;
- data cache enabled on both banks A and B, write-back mode.
- uart1, spi, ppi are enabled;
- memory configuration: stack 8kBytes minimum, heap 8MBytes minimum;
Error message on CCES:
A non-recoverable error or exception has occurred.
Description: An instruction CPLB miss has occurred without a corresponding CPLB entry.
General Type: RunTimeError
Specific Type: ICPLBMissWithoutReplacement
Error PC: 0x0bebc200
Changed the description of "PPI interrupt" to "general interrupt" as we found that other peripherals such as uart, also can cause an instruction CPLB loss at 100+ interrupt occurrances.
[edited by: yuchangz at 4:06 PM (GMT -4) on 29 Jul 2021]