Multiple interrupts triggers instruction CPLB miss.


Question: An instruction CPLB miss occurs after 125 PPI interrupts(or uart interrupts). is there a maximum amount of PPI (or other) interrupts that can occur during a program? do we have to periodically clear some registers? 

Here is a detailed description of the problem:

we are using PPI in Rx mode only to receive data. PPI is configured in interrupt callback mode:

  1. a buffer is assigned to PPI.

  2. when the buffer gets filled, it invokes the callback function.

  3. callback function determines the next available buffer to use, assigns it to the PPI, re-enables PPI, and then exits to main program.

  4. The error "An instruction CPLB miss" happens PRECISELY at the 125th occurrance of the PPI callback function. (error message below)

What we tried:

  1. we used dummy codes in PPI callback function and verified that the error is not caused by memory jams.

  2. after disabling other peripherals, we've confirmed that the error is not related to rest of our codes.

  3. also this error not only applies to PPI interrupt. If PPI is disabled, the same problem also happens to uart at approximately 100+ interrupts.

Here is a brief description of our custome board design, it features:

  - a BF527 DSP chip;

  - 64MB of external DRAM chip;

  - data cache enabled on both banks A and B, write-back mode.

  - uart1, spi, ppi are enabled;

  - memory configuration: stack 8kBytes minimum, heap 8MBytes minimum;



Error message on CCES:

A non-recoverable error or exception has occurred.
Description: An instruction CPLB miss has occurred without a corresponding CPLB entry.
General Type: RunTimeError
Specific Type: ICPLBMissWithoutReplacement
Error PC: 0x0bebc200

Changed the description of "PPI interrupt" to "general interrupt" as we found that other peripherals such as uart, also can cause an instruction CPLB loss at 100+ interrupt occurrances.
[edited by: yuchangz at 4:06 PM (GMT -4) on 29 Jul 2021]
  • update Jul 30, 2021, 1:19AM

    Some screenshots of SIC register values with breakpoint inside the PPI callback function, figure 1 shows the values of SIC remains unchanged during 1st to 124th PPI interrupts, and figure 2 is when error occurs at 125th callback.

    figure-1. SIC registers during 1st to 124th PPI interrupts.       figure-2. SIC registers values at 125th PPI interrupt.


    update Jul 30, 2021, 3:00AM

    Here is another very interesting observation:

    After putting 2 breakpoints,1 inside the PPI callback function, another inside a dummy loop in the main program, so that we jump inbetween the two breakpoints, (this way the emulation is forced to pause at the main program, and then pause again at the interrupt...), and somehow by doing this, the CPLB miss error never occurs.

    Speculation: is it possible that the error is simply caused by the emulation tool not capable of getting synced due to the periodic occurrances of the asynchronous interrupts? (P.S. we use a ICE-1000 emulator)

    Some timing specs:

    The PPI interrupts happens periodically every 2ms;

    the PPI callback has an execution time of 0.54ms;



  • 0
    •  Analog Employees 
    on Jul 30, 2021 6:25 AM in reply to yuchangz
  • 0
    •  Analog Employees 
    on Aug 2, 2021 12:11 PM in reply to yuchangz

    Hi Yuchang,

    You may check the SEQSTAT registers EXCAUSE field to check the type of error. For more information regarding SEQSTAT you may refer Blackfin processors PRM manual, which is available at the below link:

    Note that the RETX register holds the address of the instruction which caused the data CPLB fault rather than the
    address of the data that caused the failure. You have to look at the data that is accessed at the address held in RETX to figure out what the rogue access was. Possible cause of the CPLB miss without replacement in your program could be the use of an invalid address, or when there is a NULL pointer.

    We recommend to check your cache protection options. Double click the "System.svc", navigate to the 'Startup Code/LDF' tab. In the 'Startup Code' tab there are options for Instruction and Data Cache - enable or disable these as required.

    For more details please refer the below linked Ezone thread which may help you to resolve the issue:
    CPLB miss exception: