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SPU in SC571

Foster
on Jan 22, 2021

Dear all,

     In core1, I use spu for sports, and the sports works well. Then I add spu to core2 for uart, when I call funtion adi_spu_Init(), the output in core1 sports disappear , but the uart0 in core2 works well too. I don't know where is the problem. May anyone give some issues about how to use spu in both cores?

    Thanks!

  • 0
    •  Analog Employees 
    on Jan 27, 2021 12:04 PM 1 month ago

    Moved to CrossCore Embedded Studio and Add-ins Community.

  • 0
    •  Analog Employees 
    on Jan 29, 2021 12:08 PM 1 month ago

    Hello Foster,

    The adi_spu_Init() API will clear all the write protect registers and set the defalt value (0x1) to SecureP registers. Instead of calling adi_spu_Init() API, please try with calling only the adi_spu_EnableMasterSecure() to enable the secure transaction for the specific peripheral in the core2 and let us know how you gets on.

    Regards,
    Santha kumari.K

  • 0 on Feb 1, 2021 1:15 AM 28 days ago in reply to santha.vijay

    Hello Santha kumari.K,

    In core1, I called these functions,

        adi_spu_Init(0u, SpuMemory, NULL, NULL, &hSpu);

        adi_spu_EnableMasterSecure(hSpu, SPORT_0A_SPU_PID, true);

        adi_spu_EnableMasterSecure(hSpu, SPORT_0A_DDE_SPU_PID, true);

    In core2, I called these functions,

        //adi_spu_Init(0u, SpuMemory, NULL, NULL, &hSpu);

        adi_spu_EnableMasterSecure(hSpu, UART0_SPU_PID, true);

        adi_spu_EnableMasterSecure(hSpu, UART0_TX_DDE_SPU_PID, true);

        adi_spu_EnableMasterSecure(hSpu, UART0_RX_DDE_SPU_PID, true);

    When I comment out the adi_spu_Init() in core2, I'm sad to find that the UART0 did't work any more.

    I will test my projects again, and try to resolve the problem. If you have any other suggestions, please tell me.

    Thank you very much!

  • +1
    •  Analog Employees 
    on Feb 1, 2021 2:30 PM 27 days ago

    Hi,

    Our sincere apologies for the confusion caused here. If we are not calling adi_spu_Init() API, the handle will not be created. While calling adi_spu_EnableMasterSecure() API directly it will return 'ADI_SPU_INVALID_HANDLE' error. So you can't use SPU without adi_spu_Init() API.

    Since adi_spu_Init() API will clear all the write protect registers and set the default value (0x1) to SecureP registers, we can't use the API twice in the application (i.e., we can't use in both cores). Is there any specific reason for keeping SPU initialization for both peripherals in separate cores.

    Can you please try with enabling secure transaction for both SPORT and UART in a single core and let us know how you are getting on.

    Best Regards,
    Santhakumari.K

  • 0 on Feb 2, 2021 12:35 AM 27 days ago in reply to santha.vijay

    Hi,

        Yes, I enable secure transaction for both SPORT and UART in core1, then I only init SPORT in core1 and inti UART in core2. Now I can both use SPORT in core1 and UART in core2.

        I want to deal with hundreds of channels come from SPORT, it's so complex that I need to use core1 perform only as a signal processor, and core2 perform as a micro controller. 

        I'm trying to share lots of datas in l2 memory between two cores, and I have posted the problem in another topic.

    https://ez.analog.com/dsp/software-and-development-tools/cces/f/q-a/540577/l2-memory-in-sc571

        Thanks for your help!