BF706 Parity Error

Hi!

I met an error when I'm running an audio filter program based on BF706:

A non-recoverable error or exception has occurred.
  Description:   A non-speculative access has been aborted due to L1 parity Error.
  General Type:  ParityError
  Specific Type: NonSpeculativeAccessAborted
  Error PC:      0x080f00ae

I tried to debug it and found that the function adi_initComponents(),when I stepped into it, it was ok and I have no idea why.

I have checked related posts and found no solution, any help would be grateful

Best regards

Parents
  • +1
    •  Analog Employees 
    on Nov 4, 2020 11:04 AM

    Hi,

    Apologies for the delayed response.

    There are two kinds of error depend on whether the location of the parity error can be identified. The error you are facing indicates that parity error occurs from instruction memory.

    The location of a parity error can be determined by inspecting the SEQSTAT register in combination with the Instruction Memory Parity Error Status (L1IM_IPERR_STAT) or Data Memory Parity Error Status(L1DM_DPERR_STAT) registers. Please share us the screen shot of the SEQSTAT register after the error occurs.

    Please refer the chapter 'L1 Parity Protection' in the below Blackfin Programming Reference Manual:
    www.analog.com/.../ADSP-BF70x_Blackfin_Programming_Reference.pdf

    Also, could you please check the below points and update to us. This will be helpful for us to assist you better.

    1. CCES version you are using.
    2. Whether you are using custom board or Ez-kit Hardware.
    3. Are you facing this issue in specific project or with all projects.
    4. Share us the ICE details, whether you are using ICE-1000/2000 or integrated Debug Agent.
    5. Share us the sample project which reproduces this issue along with screenshot and steps.

    Regards,
    Nishanthi.V

  • Hi! sorry for this late update

    here's the screen shot of the SEQSTAT register:

    those 4 bits are all 0 and I got very confused 

    and the tips mentioned:

    1:I'm using CCES 2.9.2

    2: custom board

    3: all projects

    4: ICE-1000

    5:

    I dont know how to describe this, the error occurs at the begin of the program, at the line: adi_initComponent();

    my situation is rather the same with this post:https://ez.analog.com/dsp/blackfin-processors/bf70x/f/q-a/116999/bf706-v1-1-silicon-l1-parity-error 

    It is strange that this program works well on one computer but failed at all others.

    Thanks in advance! 

  • 0
    •  Analog Employees 
    on Jan 28, 2021 9:20 AM in reply to ZhouAdi

    Hi,

    We couldn't able to view the full results of SEQSTAT register, could you please share us the full screen shot of the SEQSTAT register which includes(NSPECABT) after the error occurs.

    We would like to suggest you to modify the code, by adding adi_initComponents() call this function early in the main() routine.
    Could you please add the code for "setup processor mode and frequency" after the  adi_initComponents(); function and let us know how you get on.
    Please refer the below code snippet.

    int main(void)

    {
    adi_initComponents();

    /* setup processor mode and frequency*/
    pwrResult = adi_pwr_Init(0, CLKIN);
    ''
    ''
    ''
    }


    There is also an anomalies available for parity error(19000004(SEQSTAT Parity Bits Cannot Be Cleared), 19000005(Parity Error Status Registers May Capture Incorrect Error Address)). Can you please check whether you are running into this kind of anomalies.

    Since you are using custom board, can you please try to simulate the issue in Ez-kit. If you have any other BF706 custom board, please try with that board and let us know how you gets on.

    Also, can you please try to load the file either with ICE-2000/ integrated Debug Agent, are you still facing the same error.

    Please share us the complete screenshot of the system information of both the machine in which CCES working and Not working PC. This can be done by pressing Windows+R to open the Run box. Type “msinfo32” into the “Open” field, and then hit Enter.
       
    Can you please share us the sample project which reproduces this issue. This will help us to assist you better.

    Regards,
    Nishanthi.V

  • Hi, thanks for the reply

    here's the full info of the SEQSTAT:

    I tried to add the adi_initComponents()  early in the main function, and it still didn't work

    And I don't have the EZ-KIT or other custom boards, besides, I only have ICE-1000

    here's the info of the PCs, the list is too long so the info of the image maybe is incomplete

    the one working(sorry for the blurred image):

    the one not working:

    and the sample project, even the simplest form of the program went wrong:

    Best regards!

Reply
  • Hi, thanks for the reply

    here's the full info of the SEQSTAT:

    I tried to add the adi_initComponents()  early in the main function, and it still didn't work

    And I don't have the EZ-KIT or other custom boards, besides, I only have ICE-1000

    here's the info of the PCs, the list is too long so the info of the image maybe is incomplete

    the one working(sorry for the blurred image):

    the one not working:

    and the sample project, even the simplest form of the program went wrong:

    Best regards!

Children
  • 0
    •  Analog Employees 
    on Feb 2, 2021 8:10 AM in reply to ZhouAdi

    Hi,

    As mentioned in the Blackfin Processor Programming Reference, under section "Detection and Notification" (Page No: 7–19 (243 / 717)), Parity errors are checked for whenever L1 memory is read. Parity checking is distributed so that all simultaneous L1 read traffic (DAG reads, instruction reads, DMA reads, and victim reads) can be simultaneously examined.

    If a parity error is detected during any L1 read, an NMI is raised. The error is immediately signaled to the processor, even if the read is speculative in nature. L1 reads by the processor are intercepted before they lead to further immediate consequence. The core will receive an NMI, be immediately stalled, and will remain stalled until it vectors to the handler in response to the NMI. This guarantees that core state is not modified based on a corrupted L1 memory state.

    For more information, please refer the "L1 Parity Protection"(Page No: 7–19 (243 / 717)) in the ADSP-BF7xx Blackfin+ Processor Programming Reference manual. The link is given below.
    www.analog.com/.../ADSP-BF70x_Blackfin_Programming_Reference.pdf

    Please note that under the Parity Error Recovery, it is mentioned that "when a parity error is detected on a L1 read, the L1 memory has already been corrupted and must be restored to a known good state. Read-only data in SRAM might be restored from a known good copy in ROM or ECC-protected L2 or L3 memory. Volatile data may need to be recomputed by rerunning a computation from a checkpointed good state. Caches can be recovered by completely invalidating the cache (by disabling and then immediately re-enabling it) so that all lines would be reacquired from non-L1 memory.

    Please try with the attached dummy project without building and let us know how you gets on. Also please try with the simulator session.

    Also, could you please check the below points and update to us. This will be helpful for us to assist you better.

    1. Since you have mentioned program works well on one computer, could you please confirm whether the same Custom board and ICE-1000, which operates correctly with the another PC.
    2. Can you please try with the latest cces vesion 2.9.3 and confirm whether the same issue occurs.

    Regards,
    Nishanthi.V

    Parity.zip