We are using ADSP-BF609 for one of our projects. The main intention in selecting this processor is the L2 SRAM and the ECC feature available with it. We want to use only Core 0 of the processor and the Core 1 will remain unused. We have a question about this.
Can the complete code (including processor start-up routines, interrupts, global variables, application code, stack and heap/cache etc.) be placed in the L2 SRAM keeping the L1 SRAM completely empty? Is this feasible..??
Could anybody pls. suggest the modifications in LDF required for this..?