BF607 L2 SRAM

Hi,

We are using ADSP-BF609 for one of our projects. The main intention in selecting this processor is the L2 SRAM and the ECC feature available with it. We want to use only Core 0 of the processor and the Core 1 will remain unused. We have a question about this.

Can the complete code (including processor start-up routines, interrupts, global variables, application code, stack and heap/cache etc.) be placed in the L2 SRAM keeping the L1 SRAM completely empty? Is this feasible..?? 

Could anybody pls. suggest the modifications in LDF required for this..?

Thank you.

Best Regards,

Pranav

  • 0
    •  Analog Employees 
    on Jun 2, 2020 5:32 AM 10 months ago
  • +1
    •  Analog Employees 
    on Sep 1, 2020 1:21 PM 7 months ago

    Hi Pranav,

    Apologies for the delayed post. We are posting here for others to benefit.

    Yes, you can place your entire code in to L2 memory based on the memory.Please refer the simple example project attached.

    By default, functions in the 'Test.c' file mapped in the output section 'L1_data_b_prio2' with in the l1 memory section 'MEM_L1_DATA_B'. If you want to map the whole object file(Test.doj) in different memory section(L2 memory),this can be done by simply adding the following line to an appropriate section in the LDF:

            INPUT_SECTIONS( Test.doj(L2_sram) )

    Your LDF should then be roughly of the form:

    PROCESSOR CORE_0
      {
        ...
        L2_general
          {
             INPUT_SECTION_ALIGN(4)
             
             INPUT_SECTIONS( test.doj(L2_sram l2_sram program noncache_code cplb_code cplb data1 voldata cplb_data vtbl constdata .edt .cht .rtti) )
          } > MEM_L2_SRAM
        ...
      }
     
    Regards,
    Nishanthi.V

    test_l2_map_fin.zip