ADAU1977 ADC SPORT configuration in DMA mode

Hello,

I'm rewrote the ADAD1979 driver (almost the same as ADAU1977 driver) in order to configure the DSP SPORT and ADAU1977 registers in I2C.

I'm using the DSP as a Master device and ADAU1977 as slave. (I2S Stereo mode)

I configured the BCLK and FSCLK using the following:

//BCLK

I'm working with SCLK0 = 112500000 so i set the BCLK to 112500000 / (35+1) = ‭3,125,000‬ (3.125Mhz) 


if(adi_sport_ConfigClock(pDevice->Sport.hSportDev,
35u,  //  SCLK0  / (35+1) 
true, // use internal CLK
!pDevice->Adc.bBClkRisingEdgeLatch,
false) != ADI_SPORT_SUCCESS)
{
/* SPORT driver error */
return (ADI_ADAU1977_SPORT_ERROR);
}

//FSCLK 

I wanted to work with 48khz but i could not get the exact freq so  ‭3,125,000‬ / 64 = 48.828 Khz

So i configured the FSCLK in level mode so each L/R channel is 32 BCLKs

if(adi_sport_ConfigFrameSync(pDevice->Sport.hSportDev,
31u,  // 31 + 2
true,
true,
true,
false,
false,
false) != ADI_SPORT_SUCCESS)

I also enabled the primary and secondary channel of the Half SPORT.

I opened the SPORT for RX in I2S mode.

/* Stereo mode */
if( adi_sport_Open ((uint32_t)pDevice->Sport.Info.SportDevNum,
(ADI_SPORT_CHANNEL)pDevice->Sport.Info.eSportChnl,
ADI_SPORT_DIR_RX,
ADI_SPORT_I2S_MODE,
pDevice->Sport.Info.pSportDevMem,
pDevice->Sport.Info.SportDevMemSize,
&pDevice->Sport.hSportDev) != ADI_SPORT_SUCCESS)
{
return (ADI_ADAU1977_SPORT_NOT_CONFIGURED);
}

I configured the DMA to work with the SPORT.

/* enable SPORT DMA */
if(adi_sport_EnableDMAMode(pDevice->Sport.hSportDev, true) != ADI_SPORT_SUCCESS)
{
return (ADI_ADAU1977_SPORT_NOT_CONFIGURED);
}


/* enable SPORT streaming */
if(adi_sport_StreamingEnable(pDevice->Sport.hSportDev, true) != ADI_SPORT_SUCCESS)
{
return (ADI_ADAU1977_SPORT_NOT_CONFIGURED);
}

/* Set DMA Transfer Size */
if(adi_sport_SetDmaTransferSize(pDevice->Sport.hSportDev, ADI_SPORT_DMA_TRANSFER_4BYTES) != ADI_SPORT_SUCCESS)
{
return (ADI_ADAU1977_SPORT_NOT_CONFIGURED);
}

I configured the ADAU1977 to work as slave and turn it on over I2C.

I also configured a callback for getting the ADC samples from DMA.

if((uint32_t)adi_adau1977_RegisterCallback(phAdau1977, (ADI_CALLBACK)callback, NULL) != 0u)
{
printf ("ADAU1977: adi_adau1977_RegisterCallback failed\n");
retCode = 1u;
}

Now i can see the BCLK and FSCLK on the bus with scope.

I also can see the sata on SD0 and SD1 coming from ADC when i turn the ADC on over I2C.

I'm working with SPORT1B so enabled the it and it's DMA for scure transactions.

/* Make SPORT 1B to generate secure transactions */
if(adi_spu_EnableMasterSecure(hSpu, SPORT_1B_SPU_PID, true) != ADI_SPU_SUCCESS)
{
DBG_MSG("Failed to enable Master secure for SPORT 1B\n");
return (ADI_SPU_FAILURE);
}

/* Make SPORT 1B DMA3 to generate secure transactions */
if(adi_spu_EnableMasterSecure(hSpu, SPORT_1B_DMA3_SPU_PID, true) != ADI_SPU_SUCCESS)
{
DBG_MSG("Failed to enable Master secure for SPORT 1B DMA3\n");
return (ADI_SPU_FAILURE);
}

For some reason i get the interrupt from DMA3 only once.

If a halt the processor and review the DMA3 registers they are reloaded and when i continue running i get another interrupt.

Why i'm doing wrong? 

How can i get continuous samples?

Please Advise.