Structure in memory accessible by all three cores

Ref: SC584

How can I create a structure in memory that is directly accessible by all three cores.  I do not want to use MCAPI.

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  • 0
    •  Analog Employees 
    on May 16, 2019 11:05 AM over 1 year ago in reply to DFitzpatrick187

    Hello,

    Please find attached a very basic project which shows that the ARM and SHARC can both read and write L1 memory. This follows the previous advice (adding a modified abstract page table to the ARM project).

    A few notes on the example:
    - this is a very naive example. We don't recommend using hard-coded addresses to share data, as is done for clarity here.
    - the apt file(apt-sc589.c) in the ARM project is modified at line 134
    - the example, when run, should print that the value at the L1 address is 1 on the SHARC core, then subsequently 2 on the ARM core. To see this, when creating your Debug Configuration, make sure you remove the Automatic Breakpoint at "main" on Core 1 (SHARC), so that the SHARC core runs without stopping when enabled from the ARM.

    For more information regarding ARM linking, please refer in CCES help:        
    CrossCore® Embedded Studio 2.8.0 > ARM® Development Tools Documentation > Cortex-A > Analog Devices ARM Toolchain Manual > Analog Devices Specific Linker Support

    Regards,
    Santha kumari.K

    Shared_memory.zip

  • Thank you for your response and example.

    This example doesn't appear to implement the 'SHARED_MEMORY{}' segment that you originally recommended.

  • 0
    •  Analog Employees 
    on May 24, 2019 2:26 PM over 1 year ago in reply to DFitzpatrick187

    Hello,

    We are working on this query. We will get back you soon

    Best regards,

    Santha kumari.K