ADSP-SC573 SHARC USB ADAU1962A TDM_Mode

Hi,

I have modified the ADC_DAC_Playback Example project to get TDM4 and also TDM8 working.

Then I added the USB Audio DEMO for ADSP-SC573 and modified the configuration settings for ADAU1962A (TDM8) and the audio is distorted.

The best way to describe this is that is sounds tinny (metalic) but all the audio channels are correct.

I have examined DBCLK, DLRCLK, DSDATA1 on the scope and this is how I confirmed that TDM8 looks to be working correctly here.

I am happy to share project if required.

Note I have sent previous requests to support & I have open support tickets but I've not had any response for a while so I'm hoping this proves more fruitful.

Thanks in advance,

Andrew

Parents
  • 0
    •  Analog Employees 
    on May 1, 2019 1:00 PM

    Hello Andrew,

    I will move this post over to the SHARC space in the forum but since I have responded I will also get emails when you post replies. I am the support person for the 1962A but not the SHARC products so I do not have this evaluation board to be able to test your project. 

    It would be helpful to see screenshots of the TDM data on a scope. Take a look at my post about how to take the screenshots: https://ez.analog.com/audio/f/discussions/3510/how-to-take-meaningful-screenshots-of-i2s-audio-signals

    Then also take a screenshot of the audio waveform. 1kHz sine wave would be good. This can sometimes give a clue as to what is going on. 

    There also can be clocking issues. Detail your clocking system and what sampling rate you are using. 

    Thanks,

    Dave T

  • Hi Dave,

    Thanks for getting back to me so quickly.

    Here's the TDM8 screenshots:

    1: FS, 2: PCM (DSDATA1)

    1: FS, 2: BCLK

    1: FS, 2: BCLK (Zoomed out).

    So as per the scope the TDM8 looks to be correct.

    Note, this is playing 8CH sine wave (sine wave is identical in each channel).

    The Sample Rate is 48kHz.

    The input audio is 16-bit, but the audio was leaking into other channels because the DAC is expecting 24-bit. So I changed the DacBuffer to 24-bit and modified the function which copies from the UsbBuffer to the DacBuffer and now the channels are correct and don't leak into each other as before.

    What specifically do you need to see with respect to the clocking system?

    In the file usbd_audio_drv_adau1979.h (Note, Config settings for ADAU1962A here...) configuration is as follows:

    /* DAC Master clock frequency */

    #define ADAU1962A_MCLK_IN (24576000u)

    /* DAC sample rate */
    #define SAMPLE_RATE (48000u)

    /* ADAU1962A SPORT config parameters */
    #define LR_B_CLK_MASTER_1962 (true)
    #define BCLK_RISING_1962 (true)

    #ifdef TDM_MODE
    #define LRCLK_HI_LO_1962 (false)
    #else
    #define LRCLK_HI_LO_1962 (true)
    #endif

    In File usbd_audio_drv_adau1979.c the following is modified:

    uint32_t adi_codec_Adau1962aInit(ADI_ADAU1962A_HANDLE *pHandle, ADI_CALLBACK pfCallback)
    {
    ADI_ADAU1962A_RESULT eResult;
    ADI_ADAU1962A_TWI_CONFIG TwiConfig;
    ADI_ADAU1962A_SPORT_CONFIG SportConfig;

    /* Open ADAU1962A device instance */
    if((eResult = adi_adau1962a_Open(ADI_CODEC_DEVICE_NUM,
    ADI_ADAU1962A_SERIAL_MODE_TDM8,
    &Adau1962aMemory,
    ADI_ADAU1962A_MEMORY_SIZE,
    pHandle)) != ADI_ADAU1962A_SUCCESS)
    {
    printf ("ADAU1962A: Failed to open ADAU1962A device instance, Error Code: 0x%08X\n", eResult);
    /* return error */
    return 1u;
    }

    /* TWI parameters required to open/configure TWI */
    TwiConfig.TwiDevNum = ADI_CODEC_TWI_DEVICE_NUM;
    TwiConfig.eTwiAddr = ADI_ADAU1962A_TWI_ADDR_04;
    TwiConfig.TwiDevMemSize = ADI_TWI_MEMORY_SIZE;
    TwiConfig.pTwiDevMem = &TwiMemory;

    /* Configure TWI */
    if ((eResult = adi_adau1962a_ConfigTwi (*pHandle, &TwiConfig)) != ADI_ADAU1962A_SUCCESS)
    {
    printf ("ADAU1962A: Failed to configure TWI, Error Code: 0x%08X\n", eResult);
    /* return error */
    return 1u;
    }

    /* SPORT parameters required to open/configure SPORT */
    SportConfig.SportDevNum = ADI_CODEC_SPORT_DEVICE_NUM;
    SportConfig.eSportChnl = ADI_ADAU1962A_SPORT_B;
    SportConfig.eSportPri = ADI_ADAU1962A_SERIAL_PORT_DSDATA1;
    SportConfig.eSportSec = ADI_ADAU1962A_SERIAL_PORT_NONE;

    SportConfig.SportDevMemSize = ADI_SPORT_DMA_MEMORY_SIZE;
    SportConfig.pSportDevMem = &Adau1962aSportMemory;

    /* Configure SPORT */
    if ((eResult = adi_adau1962a_ConfigSport (*pHandle, &SportConfig)) != ADI_ADAU1962A_SUCCESS)
    {
    printf ("ADAU1962A: Failed to configure SPORT, Error Code: 0x%08X\n", eResult);
    /* return error */
    return 1u;
    }

    /* DAC Master Power-up */
    if ((eResult = adi_adau1962a_ConfigDacPwr (*pHandle,
    ADI_ADAU1962A_CHNL_DAC_MSTR,
    ADI_ADAU1962A_DAC_PWR_LOW,
    true)) != ADI_ADAU1962A_SUCCESS)
    {
    printf ("ADAU1962A: Failed to configure DAC power, Error Code: 0x%08X\n", eResult);
    /* return error */
    return 1u;
    }

    /*
    * Configure PLL clock - DAC is clock master and drives SPORT clk and FS
    * MCLK 24.576 MHz and PLL uses MCLK
    */
    if ((eResult = adi_adau1962a_ConfigPllClk (*pHandle,
    ADAU1962A_MCLK_IN,
    ADI_ADAU1962A_MCLK_SEL_PLL,
    ADI_ADAU1962A_PLL_IN_MCLKI_XTALI)) != ADI_ADAU1962A_SUCCESS)
    {
    printf ("ADAU1962A: Failed to configure PLL clock, Error Code: 0x%08X\n", eResult);
    /* return error */
    return 1u;
    }

    /*
    * Configure serial data clock
    * DAC as clock master, External BCLK, Latch on raising edge
    * LRCLK at 50% duty cycle, MSB first, Left channel at LRCLK low
    */
    if ((eResult = adi_adau1962a_ConfigSerialClk (*pHandle,
    LR_B_CLK_MASTER_1962,
    false,
    BCLK_RISING_1962,
    /* pulse mode - true */
    true, //TDM Mode = true Else false
    false,
    LRCLK_HI_LO_1962)) != ADI_ADAU1962A_SUCCESS)
    {
    printf ("ADAU1962A: Failed to configure serial data clock, Error Code: 0x%08X\n", eResult);
    /* return error */
    return 1u;
    }

    /* Power-up PLL */
    if ((eResult = adi_adau1962a_ConfigBlockPwr (*pHandle,
    false,
    true,
    true)) != ADI_ADAU1962A_SUCCESS)
    {
    printf ("ADAU1962A: Failed to Power-up PLL, Error Code: 0x%08X\n", eResult);
    /* return error */
    return 1u;
    }

    /* Configure Sample rate */
    if ((eResult = adi_adau1962a_SetSampleRate (*pHandle, SAMPLE_RATE)) != ADI_ADAU1962A_SUCCESS)
    {
    printf ("ADAU1962A: Failed to configure Sample rate, Error Code: 0x%08X\n", eResult);
    /* return error */
    return 1u;
    }

    /* Configure Word width */
    if ((eResult = adi_adau1962a_SetWordWidth (*pHandle,
    ADI_ADAU1962A_WORD_WIDTH_24)) != ADI_ADAU1962A_SUCCESS)
    {
    printf ("ADAU1962A: Failed to configure word width, Error Code: 0x%08X\n", eResult);
    /* return error */
    return 1u;
    }

    /* Register callback */
    if ((eResult = adi_adau1962a_RegisterCallback (*pHandle,
    pfCallback,
    NULL)) != ADI_ADAU1962A_SUCCESS)
    {
    printf ("ADAU1962A: Failed to register callback, Error Code: 0x%08X\n", eResult);
    /* return error */
    return 1u;
    }

    return 0u;
    }

    The rest of the setup (config) is as the example project defines by default, I know there's something else I'm missing as the audio is tinny, but as far as I can tell the settings that make the ADC_DAC Example project work with TDM8 are all transferred into the USB project.

    Note, I have also setup the SPORT2B to mimic the ADC_DAC project - another thing I did when trying to get the audio correctly out of each channel.

    Any advice you can offer is greatly appreciated.

    Thanks in advance,

    Andrew.

  • Hi Dave, me again... (apologies)


    So we have solved one issue:
    Turns out the audio distortion was due to clipping.
    After using Reaper and reducing the levels for each audio channel by -6dB the distortion cleared.
    This led us back to the DAC and specifically the DAC Control Register 0, specifically SDATA_FMT.
    Referring to the Data sheet for the ADAU_1962a (p.30)
    The value for SDATA was set to (0x18u) I2S by the value ENUM_ADAU1962A_06_SAI_TDM8 in adi_adau1962_regs.h
    We modified this value to be Left Justified, chaning the register value to (0x58u) and the audio immediately became clear.

    The final issue is that the L/R channels remain swapped.
    Do you have any advice as to what we should be look for when trying to remedy this issue?

    Many thanks,
    Andrew

  • 0
    •  Analog Employees 
    on May 16, 2019 4:23 PM in reply to andy@sr

    Hello Andrew,

    DAC_CTRL1 register, bit 5, is for LRCLK polarity. Flip that bit and the channels will swap. 

    Dave T

  • Hi Dave,

    Thanks for getting back to me. I modified this register value from (0x43u) to (0x63u) - namely changing bit[5] as advised.

    The resulting audio was not as expected, the L/R channels remained swapped, and what I can only describe as the pulse itself is also audible.

    Processor.Tools.Support did get back to me on 05/16/2019 with a response:

    "Hi Andrew,

    We are working on this query now. We observed that DLRCLK Polarity bit is effective only when playback configuration is in I2S mode. We have verified this bit in normal ADC_DAC playback and USB audio demo code.

    We are analyzing SPORT, ADC and DAC configurations now. We will get back to you soon with an appropriate solution."

    I am awaiting their response with respect to this issue. But certainly, changing the register value for DAC_CTRL1 in this case does not seem to work.

    Many thanks,

    Andrew

  • 0
    •  Analog Employees 
    on May 20, 2019 6:49 PM in reply to andy@sr

    Hello Andrew,

    Sorry, my last response was not accurate in that I neglected to check to see what I2S format you are using. You are using a TDM-8 with a pulse type of LRCLK. For this mode of operation the LRCLK polarity will not function to swap channels. The DAC will take the first data slot and send it to DAC channel 1 and the second slot to DAC channel 2 etc. Left and Right really have no meaning in this format. Some obscure TDM formats used to still have a 50/50 duty cycle clock. Then the 8-channel TDM was organized into four stereo signals with all the odd channels when the clock is low and even when the clock is high but this does not seem to be the issue with your system. 

    So this seems to be an issue of where the SHARC is stuffing the data into the TDM stream. 

    This is where a scope can be really handy. You can see where the data is by muting or disconnecting one of the channels and seeing which one goes away on the scope. 

    I think you are fine now with regards to the DAC. The other Apps engineers should be able to help you with the SHARC side of the code. 

    Dave T

  • Hi Dave,

    Thanks for getting back to me.

    I can confirm, after using the scope that the data is in the correct slots. This was done by creating a 8ch wav file with each channel being a different constant value (e.g. ch1 = 1000, ch2 = 2000... ch8 = 8000).

    Apologies, I didn't save the screenshot but it does look as though the 8 channels are correct coming from the DAC (although L/R channels are still swapped) I therefore expect this is an issue with the SHARC as you suggest.

    For your consideration: In their latest response, I was advised by 'Processor.Tools.Support' that the ADAU1979 ADC configuration may be incorrect and was advised to modify the DLRCLK Polarity for this part in the project. I did so but this had no effect.

    I will endeavour to complete this USB audio Playback project for 8 channels of audio. I will continue my dialogue with Support and hopefully their contribution will be as effective as yours.

    Thank you for all your guidance,

    Andrew

Reply
  • Hi Dave,

    Thanks for getting back to me.

    I can confirm, after using the scope that the data is in the correct slots. This was done by creating a 8ch wav file with each channel being a different constant value (e.g. ch1 = 1000, ch2 = 2000... ch8 = 8000).

    Apologies, I didn't save the screenshot but it does look as though the 8 channels are correct coming from the DAC (although L/R channels are still swapped) I therefore expect this is an issue with the SHARC as you suggest.

    For your consideration: In their latest response, I was advised by 'Processor.Tools.Support' that the ADAU1979 ADC configuration may be incorrect and was advised to modify the DLRCLK Polarity for this part in the project. I did so but this had no effect.

    I will endeavour to complete this USB audio Playback project for 8 channels of audio. I will continue my dialogue with Support and hopefully their contribution will be as effective as yours.

    Thank you for all your guidance,

    Andrew

Children
  • +1
    •  Analog Employees 
    on Jun 25, 2019 1:35 PM in reply to andy@sr

    Hi Andrew,

    We understand that you have already contacted our private support. We are posting the final response here for others to benefit.

    While looking into the schematics we have noted that DAC1, DAC3, DAC5 and DAC7 are connected to Right channels and DAC2, DAC4, DAC6 and DAC8 are connected to left channels.

    In TDM & I2S mode, DAC1 is receiving the first channel audio (i.e., Left channel), DAC2 is receiving the second channel audio (i.e., Right channel) and so on. As the left and right channels are swapped in Hardware side, we are facing this issue.

    The root cause of this issue is alignment of RCA connectors in DAC side. DAC out1 should be connected with LEFT and so on.

    So we applied a logic while copying data from USB buffer to CODEC buffer for verifying the channel out from expected connectors.

    Please replace the attached file in the file path for getting audio out from expected channels output

    C:\Analog Devices\uCUSBD_Class_Audio-Rel2.6.0\uC-USBD-audio\common\Class\Audio\Drivers\Codec\adi_adau1979

    Regards,
    Santha kumari.K

    usbd_audio_drv_adau1979.zip