ADSP-SC573 SHARC USB ADAU1962A TDM_Mode

Hi,

I have modified the ADC_DAC_Playback Example project to get TDM4 and also TDM8 working.

Then I added the USB Audio DEMO for ADSP-SC573 and modified the configuration settings for ADAU1962A (TDM8) and the audio is distorted.

The best way to describe this is that is sounds tinny (metalic) but all the audio channels are correct.

I have examined DBCLK, DLRCLK, DSDATA1 on the scope and this is how I confirmed that TDM8 looks to be working correctly here.

I am happy to share project if required.

Note I have sent previous requests to support & I have open support tickets but I've not had any response for a while so I'm hoping this proves more fruitful.

Thanks in advance,

Andrew

Parents
  • 0
    •  Analog Employees 
    on May 1, 2019 1:00 PM

    Hello Andrew,

    I will move this post over to the SHARC space in the forum but since I have responded I will also get emails when you post replies. I am the support person for the 1962A but not the SHARC products so I do not have this evaluation board to be able to test your project. 

    It would be helpful to see screenshots of the TDM data on a scope. Take a look at my post about how to take the screenshots: https://ez.analog.com/audio/f/discussions/3510/how-to-take-meaningful-screenshots-of-i2s-audio-signals

    Then also take a screenshot of the audio waveform. 1kHz sine wave would be good. This can sometimes give a clue as to what is going on. 

    There also can be clocking issues. Detail your clocking system and what sampling rate you are using. 

    Thanks,

    Dave T

  • Hi Dave,

    Thanks for getting back to me so quickly.

    Here's the TDM8 screenshots:

    1: FS, 2: PCM (DSDATA1)

    1: FS, 2: BCLK

    1: FS, 2: BCLK (Zoomed out).

    So as per the scope the TDM8 looks to be correct.

    Note, this is playing 8CH sine wave (sine wave is identical in each channel).

    The Sample Rate is 48kHz.

    The input audio is 16-bit, but the audio was leaking into other channels because the DAC is expecting 24-bit. So I changed the DacBuffer to 24-bit and modified the function which copies from the UsbBuffer to the DacBuffer and now the channels are correct and don't leak into each other as before.

    What specifically do you need to see with respect to the clocking system?

    In the file usbd_audio_drv_adau1979.h (Note, Config settings for ADAU1962A here...) configuration is as follows:

    /* DAC Master clock frequency */

    #define ADAU1962A_MCLK_IN (24576000u)

    /* DAC sample rate */
    #define SAMPLE_RATE (48000u)

    /* ADAU1962A SPORT config parameters */
    #define LR_B_CLK_MASTER_1962 (true)
    #define BCLK_RISING_1962 (true)

    #ifdef TDM_MODE
    #define LRCLK_HI_LO_1962 (false)
    #else
    #define LRCLK_HI_LO_1962 (true)
    #endif

    In File usbd_audio_drv_adau1979.c the following is modified:

    uint32_t adi_codec_Adau1962aInit(ADI_ADAU1962A_HANDLE *pHandle, ADI_CALLBACK pfCallback)
    {
    ADI_ADAU1962A_RESULT eResult;
    ADI_ADAU1962A_TWI_CONFIG TwiConfig;
    ADI_ADAU1962A_SPORT_CONFIG SportConfig;

    /* Open ADAU1962A device instance */
    if((eResult = adi_adau1962a_Open(ADI_CODEC_DEVICE_NUM,
    ADI_ADAU1962A_SERIAL_MODE_TDM8,
    &Adau1962aMemory,
    ADI_ADAU1962A_MEMORY_SIZE,
    pHandle)) != ADI_ADAU1962A_SUCCESS)
    {
    printf ("ADAU1962A: Failed to open ADAU1962A device instance, Error Code: 0x%08X\n", eResult);
    /* return error */
    return 1u;
    }

    /* TWI parameters required to open/configure TWI */
    TwiConfig.TwiDevNum = ADI_CODEC_TWI_DEVICE_NUM;
    TwiConfig.eTwiAddr = ADI_ADAU1962A_TWI_ADDR_04;
    TwiConfig.TwiDevMemSize = ADI_TWI_MEMORY_SIZE;
    TwiConfig.pTwiDevMem = &TwiMemory;

    /* Configure TWI */
    if ((eResult = adi_adau1962a_ConfigTwi (*pHandle, &TwiConfig)) != ADI_ADAU1962A_SUCCESS)
    {
    printf ("ADAU1962A: Failed to configure TWI, Error Code: 0x%08X\n", eResult);
    /* return error */
    return 1u;
    }

    /* SPORT parameters required to open/configure SPORT */
    SportConfig.SportDevNum = ADI_CODEC_SPORT_DEVICE_NUM;
    SportConfig.eSportChnl = ADI_ADAU1962A_SPORT_B;
    SportConfig.eSportPri = ADI_ADAU1962A_SERIAL_PORT_DSDATA1;
    SportConfig.eSportSec = ADI_ADAU1962A_SERIAL_PORT_NONE;

    SportConfig.SportDevMemSize = ADI_SPORT_DMA_MEMORY_SIZE;
    SportConfig.pSportDevMem = &Adau1962aSportMemory;

    /* Configure SPORT */
    if ((eResult = adi_adau1962a_ConfigSport (*pHandle, &SportConfig)) != ADI_ADAU1962A_SUCCESS)
    {
    printf ("ADAU1962A: Failed to configure SPORT, Error Code: 0x%08X\n", eResult);
    /* return error */
    return 1u;
    }

    /* DAC Master Power-up */
    if ((eResult = adi_adau1962a_ConfigDacPwr (*pHandle,
    ADI_ADAU1962A_CHNL_DAC_MSTR,
    ADI_ADAU1962A_DAC_PWR_LOW,
    true)) != ADI_ADAU1962A_SUCCESS)
    {
    printf ("ADAU1962A: Failed to configure DAC power, Error Code: 0x%08X\n", eResult);
    /* return error */
    return 1u;
    }

    /*
    * Configure PLL clock - DAC is clock master and drives SPORT clk and FS
    * MCLK 24.576 MHz and PLL uses MCLK
    */
    if ((eResult = adi_adau1962a_ConfigPllClk (*pHandle,
    ADAU1962A_MCLK_IN,
    ADI_ADAU1962A_MCLK_SEL_PLL,
    ADI_ADAU1962A_PLL_IN_MCLKI_XTALI)) != ADI_ADAU1962A_SUCCESS)
    {
    printf ("ADAU1962A: Failed to configure PLL clock, Error Code: 0x%08X\n", eResult);
    /* return error */
    return 1u;
    }

    /*
    * Configure serial data clock
    * DAC as clock master, External BCLK, Latch on raising edge
    * LRCLK at 50% duty cycle, MSB first, Left channel at LRCLK low
    */
    if ((eResult = adi_adau1962a_ConfigSerialClk (*pHandle,
    LR_B_CLK_MASTER_1962,
    false,
    BCLK_RISING_1962,
    /* pulse mode - true */
    true, //TDM Mode = true Else false
    false,
    LRCLK_HI_LO_1962)) != ADI_ADAU1962A_SUCCESS)
    {
    printf ("ADAU1962A: Failed to configure serial data clock, Error Code: 0x%08X\n", eResult);
    /* return error */
    return 1u;
    }

    /* Power-up PLL */
    if ((eResult = adi_adau1962a_ConfigBlockPwr (*pHandle,
    false,
    true,
    true)) != ADI_ADAU1962A_SUCCESS)
    {
    printf ("ADAU1962A: Failed to Power-up PLL, Error Code: 0x%08X\n", eResult);
    /* return error */
    return 1u;
    }

    /* Configure Sample rate */
    if ((eResult = adi_adau1962a_SetSampleRate (*pHandle, SAMPLE_RATE)) != ADI_ADAU1962A_SUCCESS)
    {
    printf ("ADAU1962A: Failed to configure Sample rate, Error Code: 0x%08X\n", eResult);
    /* return error */
    return 1u;
    }

    /* Configure Word width */
    if ((eResult = adi_adau1962a_SetWordWidth (*pHandle,
    ADI_ADAU1962A_WORD_WIDTH_24)) != ADI_ADAU1962A_SUCCESS)
    {
    printf ("ADAU1962A: Failed to configure word width, Error Code: 0x%08X\n", eResult);
    /* return error */
    return 1u;
    }

    /* Register callback */
    if ((eResult = adi_adau1962a_RegisterCallback (*pHandle,
    pfCallback,
    NULL)) != ADI_ADAU1962A_SUCCESS)
    {
    printf ("ADAU1962A: Failed to register callback, Error Code: 0x%08X\n", eResult);
    /* return error */
    return 1u;
    }

    return 0u;
    }

    The rest of the setup (config) is as the example project defines by default, I know there's something else I'm missing as the audio is tinny, but as far as I can tell the settings that make the ADC_DAC Example project work with TDM8 are all transferred into the USB project.

    Note, I have also setup the SPORT2B to mimic the ADC_DAC project - another thing I did when trying to get the audio correctly out of each channel.

    Any advice you can offer is greatly appreciated.

    Thanks in advance,

    Andrew.

  • 0
    •  Analog Employees 
    on May 2, 2019 5:25 PM in reply to andy@sr

    Hello Andrew,

    These are SHARC register settings. I am only concerned with the DAC. I support the DAC and wrote that datasheet. I hope someone else from the SHARC DSP support group will look into the other settings and questions you have. 

    The LRCLK is set with the DAC Control Register 1 located at address 0x07 and bit 6 will set it to pulse or 50/50% duty cycle. 

    Here is your code segment that suggests that it could be set to 50/50. This is what I mean that I have no idea what is actually being executed. 

    * Configure serial data clock
    * DAC as clock master, External BCLK, Latch on raising edge
    * LRCLK at 50% duty cycle, MSB first, Left channel at LRCLK low
    */
    if ((eResult = adi_adau1962a_ConfigSerialClk (*pHandle,
    LR_B_CLK_MASTER_1962,
    false,
    BCLK_RISING_1962,
    /* pulse mode - true */
    true, //TDM Mode = true Else false
    false,
    LRCLK_HI_LO_1962)) != ADI_ADAU1962A_SUCCESS)
    {

    I am just trying to be certain you are setting the DAC to the correct setting for the format of the data you are sending and that you are setting the PLL correctly etc. The fact that you are hearing some audio means you are probably not far off. 

    So send me the DAC register settings that are being sent to the DAC. Another thing you could do is to read back all the registers after configuring to see what they are actually set to. 

    Thanks,

    Dave T

  • Hi Dave,

    Apologies for my ignorance, I am only a few months into working with hardware, so I thoroughly appreciate you taking the time to aide me in whatever way possible.

    For explicity's sake I have modified function adi_adau1962a_ConfigSerialClk to show bool values and settings (image attached as it's easier to read than the code pasted in):

    I think you mean DAC register settings in file adi_adau1962a_regs.h, correct? if so, see below:

    If not, can you please detail how to get the information you need?

    Many Thanks,

    Andrew

    /* PLL and Clock control 0 Register field definitions (ADI_ADAU1962A_REG_PLL_CLK_CTRL0) */
    #define BITM_ADAU1962A_00_PLL_IN (0xC0u) /* PLL Input */
    #define ENUM_ADAU1962A_00_PLL_IN_DLRCLK (0x40u) /* DLRCLK */
    #define ENUM_ADAU1962A_00_PLL_IN_MCLKI (0x00u) /* MCLKI/XI */

    #define BITM_ADAU1962A_00_XTAL_SET (0x30u) /* XTALO pin status */
    #define ENUM_ADAU1962A_00_XTAL_OSC_OFF (0x30u) /* XTAL Oscillator Off */
    #define ENUM_ADAU1962A_00_XTAL_OSC_ON (0x00u) /* XTAL oscillator On */

    #define BITM_ADAU1962A_00_SOFT_RST (0x08u) /* Soft-Reset control */
    #define ENUM_ADAU1962A_00_SOFT_RST_EN (0x08u) /* Enable Soft-Reset */
    #define ENUM_ADAU1962A_00_SOFT_RST_CLR (0x00u) /* Clear Soft-Reset */

    #define BITP_ADAU1962A_00_MCLK_SEL (1u) /* MCLK Select position */
    #define BITM_ADAU1962A_00_MCLK_SEL (0x06u) /* MCLK pin functionality (PLL active) Mask */
    #define ENUM_ADAU1962A_00_MCLK_SEL_768 (0x06u) /* INPUT 768 (x 44.1 kHz or 48 kHz) */
    #define ENUM_ADAU1962A_00_MCLK_SEL_512 (0x04u) /* INPUT 512 (x 44.1 kHz or 48 kHz) */
    #define ENUM_ADAU1962A_00_MCLK_SEL_384 (0x02u) /* INPUT 384 (x 44.1 kHz or 48 kHz) */
    #define ENUM_ADAU1962A_00_MCLK_SEL_256 (0x00u) /* INPUT 256 (x 44.1 kHz or 48 kHz) */

    #define BITM_ADAU1962A_00_MSTR_PWR (0x01u) /* Master Power-Up Control */
    #define ENUM_ADAU1962A_00_MSTR_PWR_UP (0x01u) /* Master Power-Up */
    #define ENUM_ADAU1962A_00_MSTR_PWR_DN (0x00u) /* Master Power-Down */

    /* PLL and Clock control 1 Register field definitions (ADI_ADAU1962A_REG_PLL_CLK_CTRL1) */
    #define BITM_ADAU1962A_01_LOPWR_MODE (0xC0u) /* Global Power/Performance Adjust */
    #define ENUM_ADAU1962A_01_LOPWR_MODE_LOWEST (0xC0u) /* Lowest Power */
    #define ENUM_ADAU1962A_01_LOPWR_MODE_LOWER (0x80u) /* Lower Power */
    #define ENUM_ADAU1962A_01_LOPWR_MODE_I2C (0x00u) /* I2C Register Settings */

    #define BITM_ADAU1962A_01_MCLKO_SEL (0x30u) /* MCLK Output Frequency */
    #define ENUM_ADAU1962A_01_MCLKO_DIS (0x30u) /* MCLKO Pin Disabled */
    #define ENUM_ADAU1962A_01_MCLKO_MCLKI (0x20u) /* Buffered MCLKI */
    #define ENUM_ADAU1962A_01_MCLKO_8_12MHZ (0x10u) /* 8 MHz to 12 MHz scaled by fs */
    #define ENUM_ADAU1962A_01_MCLKO_4_6MHZ (0x00u) /* 4 MHz to 6 MHz scaled by fs */

    #define BITM_ADAU1962A_01_PLL_MUTE (0x08u) /* PLL Automute Enable/Lock */
    #define ENUM_ADAU1962A_01_PLL_MUTE_EN (0x08u) /* DAC Automute on PLL Unlock */
    #define ENUM_ADAU1962A_01_PLL_MUTE_DIS (0x00u) /* No DAC Automute */

    #define BITM_ADAU1962A_01_PLL_LOCK (0x04u) /* PLL Lock Indicator */
    #define ENUM_ADAU1962A_01_PLL_LOCKED (0x00u) /* PLL Locked */

    #define BITM_ADAU1962A_01_VREF_EN (0x02u) /* Internal Voltage Reference Enable */
    #define ENUM_ADAU1962A_01_VREF_EN (0x02u) /* VREF Enabled */
    #define ENUM_ADAU1962A_01_VREF_DIS (0x00u) /* VREF Disabled */

    #define BITM_ADAU1962A_01_DAC_CLK_SEL (0x01u) /* DAC Clock Select */
    #define ENUM_ADAU1962A_01_DAC_CLK_MCLKI (0x01u) /* MCLK from MCLKI or XTALI as DAC Clock Source */
    #define ENUM_ADAU1962A_01_DAC_CLK_PLL (0x00u) /* PLL as DAC Clock Source */

    /* Block Power-down and Thermal Sensor Control 1 Register field definitions (ADI_ADAU1962A_REG_PDN_THRMSENS_CTRL_1) */
    #define BITM_ADAU1962A_02_THRM_RATE (0xC0u) /* Conversion Time Interval */
    #define ENUM_ADAU1962A_02_THRM_RATE_2S (0xC0u) /* 2 sec/Conversion */
    #define ENUM_ADAU1962A_02_THRM_RATE_1S (0x80u) /* 1 sec/Conversion */
    #define ENUM_ADAU1962A_02_THRM_RATE_0_5_S (0x40u) /* One-Shot Mode */
    #define ENUM_ADAU1962A_02_THRM_RATE_4S (0x00u) /* 4 sec/Conversion */

    #define BITM_ADAU1962A_02_THRM_MODE (0x20u) /* One-Shot Conversion Mode */
    #define ENUM_ADAU1962A_02_THRM_MODE_ONE_SHOT (0x20u) /* One-Shot Mode */
    #define ENUM_ADAU1962A_02_THRM_MODE_CONTINUOUS (0x00u) /* Continuous Operation */

    #define BITM_ADAU1962A_02_THRM_GO (0x10u) /* One-Shot Conversion Mode */
    #define ENUM_ADAU1962A_02_THRM_GO_CONVERT (0x10u) /* Convert Temperature */
    #define ENUM_ADAU1962A_02_THRM_GO_RESET (0x00u) /* Reset */

    #define BITM_ADAU1962A_02_TS_PDN (0x04u) /* Temperature Sensor Power-Down */
    #define ENUM_ADAU1962A_02_TS_PDN_PDN (0x04u) /* Temperature Sensor Power-Down */
    #define ENUM_ADAU1962A_02_TS_PDN_NORMAL (0x00u) /* Temperature Sensor Normal Operation */

    #define BITM_ADAU1962A_02_PLL_PDN (0x02u) /* PLL Power-Down */
    #define ENUM_ADAU1962A_02_PLL_PDN_PDN (0x02u) /* PLL Power-Down */
    #define ENUM_ADAU1962A_02_PLL_PDN_NORMAL (0x00u) /* PLL Normal Operation */

    #define BITM_ADAU1962A_02_VREG_PDN (0x01u) /* Voltage Regulator Power-Down */
    #define ENUM_ADAU1962A_02_VREG_PDN_PDN (0x01u) /* Voltage Regulator Power-Down */
    #define ENUM_ADAU1962A_02_VREG_PDN_NORMAL (0x00u) /* Voltage Regulator Normal Operation */

    /* Bit mask for power-down control */
    #define BITM_ADAU1962A_02_PDN_CTRL (BITM_ADAU1962A_02_TS_PDN |\
    BITM_ADAU1962A_02_PLL_PDN |\
    BITM_ADAU1962A_02_VREG_PDN)

    /* Power-Down control 2 Register field definitions (ADI_ADAU1962A_REG_PDN_CTRL2) */
    #define BITM_ADAU1962A_03_DAC_PDN (0x01u) /* Power-Down DAC Channel */
    #define ENUM_ADAU1962A_03_DAC_PDN_PDN (0x01u) /* Power-Down DAC Channel */
    #define ENUM_ADAU1962A_03_DAC_PDN_NORMAL (0x00u) /* Normal Operation */

    /* DAC control 0 Register field definitions (ADI_ADAU1962A_REG_DAC_CTRL0) */
    #define BITM_ADAU1962A_06_SDATA_FMT (0xC0u) /* SDATA Format */
    #define ENUM_ADAU1962A_06_SDATA_FMT_I2S (0x00u) /* I2S, 1 BCLK Cycle Delay */

    #define BITM_ADAU1962A_06_SAI (0x38u) /* Serial Audio Interface */
    #define ENUM_ADAU1962A_06_SAI_TDM16 (0x20u) /* TDM16—Single Line (48 kHz) */
    #define ENUM_ADAU1962A_06_SAI_TDM8 (0x18u) /* TDM8—Dual Line */
    #define ENUM_ADAU1962A_06_SAI_TDM4 (0x10u) /* TDM4—Quad Line */
    #define ENUM_ADAU1962A_06_SAI_TDM2 (0x08u) /* TDM2—Octal Line */
    #define ENUM_ADAU1962A_06_SAI_STEREO (0x00u) /* Stereo (I2S, LJ, RJ) */

    #define BITP_ADAU1962A_06_FS (1u) /* Sample Rate Select */
    #define BITM_ADAU1962A_06_FS (0x06u) /* Mask for Sample Rate Select */
    #define ENUM_ADAU1962A_06_FS_128_176_192_LOW (0x06u) /* 128 kHz/176.4 kHz/192 kHz Low Propagation Delay */
    #define ENUM_ADAU1962A_06_FS_128_176_192 (0x04u) /* 128 kHz/176.4 kHz/192 kHz */
    #define ENUM_ADAU1962A_06_FS_64_88_96 (0x02u) /* 64 kHz/88.2 kHz/96 kHz */
    #define ENUM_ADAU1962A_06_FS_32_44_48 (0x00u) /* 32 kHz/44.1 kHz/48 kHz */

    #define BITM_ADAU1962A_06_MMUTE (0x01u) /* Master Mute */
    #define ENUM_ADAU1962A_06_MMUTE_EN (0x01u) /* All Channels Muted */
    #define ENUM_ADAU1962A_06_MMUTE_DIS (0x00u) /* Normal Operation */

    /* DAC control 1 Register field definitions (ADI_ADAU1962A_REG_DAC_CTRL1) */
    #define BITM_ADAU1962A_07_BCLK_GEN (0x80u) /* DBCLK Generation */
    #define ENUM_ADAU1962A_07_BCLK_GEN_INTERNAL (0x80u) /* Internal DBCLK Generation */
    #define ENUM_ADAU1962A_07_BCLK_GEN_NORMAL (0x00u) /* Normal Operation—DBCLK */

    #define BITM_ADAU1962A_07_LRCLK_MODE (0x40u) /* DLRCLK Mode Select. Only Valid for TDM modes */
    #define ENUM_ADAU1962A_07_LRCLK_PULSE (0x40u) /* Pulse mode */
    #define ENUM_ADAU1962A_07_LRCLK_50_50 (0x00u) /* 50% Duty Cycle DLRCLK */

    #define BITM_ADAU1962A_07_LRCLK_POL (0x00u) /* DLRCLK Polarity. Allows the swapping of data between channels */
    #define ENUM_ADAU1962A_07_LRCLK_POL_INVERT (0x20u) /* Left/Odd channels are DLRCLK High (Inverted) */
    #define ENUM_ADAU1962A_07_LRCLK_POL_NORMAL (0x00u) /* Left/Odd channels are DLRCLK Low (Normal) */

    #define BITM_ADAU1962A_07_SAI_MSB (0x10u) /* MSB Position */
    #define ENUM_ADAU1962A_07_SAI_LSB_FIRST (0x10u) /* LSB First DSDATA */
    #define ENUM_ADAU1962A_07_SAI_MSB_FIRST (0x00u) /* MSB First DSDATA */

    #define BITM_ADAU1962A_07_BCLK_RATE (0x04u) /* DBCLK Rate. Number of DBCLK cycles per DLRCLK frame */
    #define ENUM_ADAU1962A_07_BCLK_RATE_16CYCLES (0x04u) /* 16 Cycles per Frame */
    #define ENUM_ADAU1962A_07_BCLK_RATE_32CYCLES (0x00u) /* 32 Cycles per Frame */

    #define BITM_ADAU1962A_07_BCLK_EDGE (0x02u) /* DBCLK Active Edge */
    #define ENUM_ADAU1962A_07_BCLK_FALLING_EDGE (0x02u) /* Latch on Falling Edge */
    #define ENUM_ADAU1962A_07_BCLK_RISING_EDGE (0x00u) /* Latch on Rising Edge */

    #define BITM_ADAU1962A_07_SAI_MS (0x01u) /* Serial Interface Master */
    #define ENUM_ADAU1962A_07_SAI_MASTER (0x01u) /* DLRCLK/DBCLK Master */
    #define ENUM_ADAU1962A_07_SAI_SLAVE (0x00u) /* DLRCLK/DBCLK Slave */

    /* DAC control 2 Register field definitions (ADI_ADAU1962A_REG_DAC_CTRL2) */
    #define BITM_ADAU1962A_08_BCLK_TDMC (0x20u) /* DBCLK Rate in TDM Mode */
    #define ENUM_ADAU1962A_08_BCLK_TDMC_16 (0x20u) /* 16 BCLK cycles/channel slot */
    #define ENUM_ADAU1962A_08_BCLK_TDMC_32 (0x00u) /* 32 BCLK cycles/channel slot */

    #define BITM_ADAU1962A_08_DAC_POL (0x10u) /* DAC Output Polarity. This is a global switch of DAC polarity */
    #define ENUM_ADAU1962A_08_DAC_POL_INVERT (0x10u) /* Inverted DAC Output */
    #define ENUM_ADAU1962A_08_DAC_POL_NON_INVERT (0x00u) /* NonInverted DAC Output */

    #define BITM_ADAU1962A_08_AUTO_MUTE_EN (0x04u) /* Automute Enable */
    #define ENUM_ADAU1962A_08_AUTO_MUTE_EN (0x04u) /* Auto-Zero Input Mute Enabled */
    #define ENUM_ADAU1962A_08_AUTO_MUTE_DIS (0x00u) /* Auto-Zero Input Mute Disabled */

    #define BITM_ADAU1962A_08_DAC_OSR (0x02u) /* DAC Oversampling Rate. OSR selection */
    #define ENUM_ADAU1962A_08_DAC_OSR_128 (0x02u) /* 128 × fs DAC Oversampling */
    #define ENUM_ADAU1962A_08_DAC_OSR_256 (0x00u) /* 256 × fs DAC Oversampling */

    #define BITM_ADAU1962A_08_DE_EMP_EN (0x01u) /* De-Emphasis Enable */
    #define ENUM_ADAU1962A_08_DE_EMP_EN (0x01u) /* De-Emphasis Enabled */
    #define ENUM_ADAU1962A_08_DE_EMP_DIS (0x00u) /* No De-Emphasis/Flat */

    /* DAC Individual channel mutes 1 Register field definitions (ADI_ADAU1962A_REG_DAC_MUTE1) */
    #define BITM_ADAU1962A_09_DAC_MUTE (0x01u) /* Mute DAC Channel */
    #define ENUM_ADAU1962A_09_DAC_MUTE_EN (0x01u) /* Mute DAC Channel */
    #define ENUM_ADAU1962A_09_DAC_MUTE_DIS (0x00u) /* Normal Operation, Mute disabled */

    /* Pad strength Register field definitions (ADI_ADAU1962A_REG_PAD_STRGTH) */
    #define BITM_ADAU1962A_1C_PAD_DRV (0x20u) /* Output Pad Drive Strength Control */
    #define ENUM_ADAU1962A_1C_PAD_DRV_8MA (0x20u) /* 8 mA Drive for All Pads */
    #define ENUM_ADAU1962A_1C_PAD_DRV_4MA (0x00u) /* 4 mA Drive for All Pads */

    /* DAC Power adjust 1 Register field definitions (ADI_ADAU1962A_REG_DAC_POWER1) */
    #define BITM_ADAU1962A_1D_DAC_POWER (0x03u) /* DAC Power Control */
    #define ENUM_ADAU1962A_1D_DAC_GOOD_PERF (0x03u) /* Good Performance */
    #define ENUM_ADAU1962A_1D_DAC_BEST_PERF (0x02u) /* Best Performance */
    #define ENUM_ADAU1962A_1D_DAC_LOWEST_POWER (0x01u) /* Lowest Power */
    #define ENUM_ADAU1962A_1D_DAC_LOW_POWER (0x00u) /* Low Power */

  • 0
    •  Analog Employees 
    on May 2, 2019 7:10 PM in reply to andy@sr

    Hello Andrew,

    My apologies with not being clear enough.

    Read the registers in the DAC, registers at addresses 0x00 to 0x1F and send me the results. No code, just 8-bit hex numbers. There are 27 registers. 

    All the defines you listed are for writing to the DAC. I want to know what the result was once all the writes have happened. 

    Thanks,

    Dave T

  • Hi Dave,

    Apologies from my .xlsx document being incorrect, I have been checking over the registers and it seems the values outputted by the function I used wasn't accurate, something I tried to confirm and avoid.

    That said, I hope I haven't wasted any of your time by having you check those values.

    I found an example of where to read the registers and hopefully this better explains what I'm actually getting and allows you to offer some helpful advice.

    Kind regards,

    Andrew

  • Hi Dave, me again... (apologies)


    So we have solved one issue:
    Turns out the audio distortion was due to clipping.
    After using Reaper and reducing the levels for each audio channel by -6dB the distortion cleared.
    This led us back to the DAC and specifically the DAC Control Register 0, specifically SDATA_FMT.
    Referring to the Data sheet for the ADAU_1962a (p.30)
    The value for SDATA was set to (0x18u) I2S by the value ENUM_ADAU1962A_06_SAI_TDM8 in adi_adau1962_regs.h
    We modified this value to be Left Justified, chaning the register value to (0x58u) and the audio immediately became clear.

    The final issue is that the L/R channels remain swapped.
    Do you have any advice as to what we should be look for when trying to remedy this issue?

    Many thanks,
    Andrew

Reply
  • Hi Dave, me again... (apologies)


    So we have solved one issue:
    Turns out the audio distortion was due to clipping.
    After using Reaper and reducing the levels for each audio channel by -6dB the distortion cleared.
    This led us back to the DAC and specifically the DAC Control Register 0, specifically SDATA_FMT.
    Referring to the Data sheet for the ADAU_1962a (p.30)
    The value for SDATA was set to (0x18u) I2S by the value ENUM_ADAU1962A_06_SAI_TDM8 in adi_adau1962_regs.h
    We modified this value to be Left Justified, chaning the register value to (0x58u) and the audio immediately became clear.

    The final issue is that the L/R channels remain swapped.
    Do you have any advice as to what we should be look for when trying to remedy this issue?

    Many thanks,
    Andrew

Children
  • 0
    •  Analog Employees 
    on May 16, 2019 4:23 PM in reply to andy@sr

    Hello Andrew,

    DAC_CTRL1 register, bit 5, is for LRCLK polarity. Flip that bit and the channels will swap. 

    Dave T

  • Hi Dave,

    Thanks for getting back to me. I modified this register value from (0x43u) to (0x63u) - namely changing bit[5] as advised.

    The resulting audio was not as expected, the L/R channels remained swapped, and what I can only describe as the pulse itself is also audible.

    Processor.Tools.Support did get back to me on 05/16/2019 with a response:

    "Hi Andrew,

    We are working on this query now. We observed that DLRCLK Polarity bit is effective only when playback configuration is in I2S mode. We have verified this bit in normal ADC_DAC playback and USB audio demo code.

    We are analyzing SPORT, ADC and DAC configurations now. We will get back to you soon with an appropriate solution."

    I am awaiting their response with respect to this issue. But certainly, changing the register value for DAC_CTRL1 in this case does not seem to work.

    Many thanks,

    Andrew

  • 0
    •  Analog Employees 
    on May 20, 2019 6:49 PM in reply to andy@sr

    Hello Andrew,

    Sorry, my last response was not accurate in that I neglected to check to see what I2S format you are using. You are using a TDM-8 with a pulse type of LRCLK. For this mode of operation the LRCLK polarity will not function to swap channels. The DAC will take the first data slot and send it to DAC channel 1 and the second slot to DAC channel 2 etc. Left and Right really have no meaning in this format. Some obscure TDM formats used to still have a 50/50 duty cycle clock. Then the 8-channel TDM was organized into four stereo signals with all the odd channels when the clock is low and even when the clock is high but this does not seem to be the issue with your system. 

    So this seems to be an issue of where the SHARC is stuffing the data into the TDM stream. 

    This is where a scope can be really handy. You can see where the data is by muting or disconnecting one of the channels and seeing which one goes away on the scope. 

    I think you are fine now with regards to the DAC. The other Apps engineers should be able to help you with the SHARC side of the code. 

    Dave T

  • Hi Dave,

    Thanks for getting back to me.

    I can confirm, after using the scope that the data is in the correct slots. This was done by creating a 8ch wav file with each channel being a different constant value (e.g. ch1 = 1000, ch2 = 2000... ch8 = 8000).

    Apologies, I didn't save the screenshot but it does look as though the 8 channels are correct coming from the DAC (although L/R channels are still swapped) I therefore expect this is an issue with the SHARC as you suggest.

    For your consideration: In their latest response, I was advised by 'Processor.Tools.Support' that the ADAU1979 ADC configuration may be incorrect and was advised to modify the DLRCLK Polarity for this part in the project. I did so but this had no effect.

    I will endeavour to complete this USB audio Playback project for 8 channels of audio. I will continue my dialogue with Support and hopefully their contribution will be as effective as yours.

    Thank you for all your guidance,

    Andrew

  • +1
    •  Analog Employees 
    on Jun 25, 2019 1:35 PM in reply to andy@sr

    Hi Andrew,

    We understand that you have already contacted our private support. We are posting the final response here for others to benefit.

    While looking into the schematics we have noted that DAC1, DAC3, DAC5 and DAC7 are connected to Right channels and DAC2, DAC4, DAC6 and DAC8 are connected to left channels.

    In TDM & I2S mode, DAC1 is receiving the first channel audio (i.e., Left channel), DAC2 is receiving the second channel audio (i.e., Right channel) and so on. As the left and right channels are swapped in Hardware side, we are facing this issue.

    The root cause of this issue is alignment of RCA connectors in DAC side. DAC out1 should be connected with LEFT and so on.

    So we applied a logic while copying data from USB buffer to CODEC buffer for verifying the channel out from expected connectors.

    Please replace the attached file in the file path for getting audio out from expected channels output

    C:\Analog Devices\uCUSBD_Class_Audio-Rel2.6.0\uC-USBD-audio\common\Class\Audio\Drivers\Codec\adi_adau1979

    Regards,
    Santha kumari.K

    usbd_audio_drv_adau1979.zip