ADSP-SC573 SHARC USB ADAU1962A TDM_Mode

Hi,

I have modified the ADC_DAC_Playback Example project to get TDM4 and also TDM8 working.

Then I added the USB Audio DEMO for ADSP-SC573 and modified the configuration settings for ADAU1962A (TDM8) and the audio is distorted.

The best way to describe this is that is sounds tinny (metalic) but all the audio channels are correct.

I have examined DBCLK, DLRCLK, DSDATA1 on the scope and this is how I confirmed that TDM8 looks to be working correctly here.

I am happy to share project if required.

Note I have sent previous requests to support & I have open support tickets but I've not had any response for a while so I'm hoping this proves more fruitful.

Thanks in advance,

Andrew

  • 0
    •  Analog Employees 
    on May 1, 2019 1:00 PM

    Hello Andrew,

    I will move this post over to the SHARC space in the forum but since I have responded I will also get emails when you post replies. I am the support person for the 1962A but not the SHARC products so I do not have this evaluation board to be able to test your project. 

    It would be helpful to see screenshots of the TDM data on a scope. Take a look at my post about how to take the screenshots: https://ez.analog.com/audio/f/discussions/3510/how-to-take-meaningful-screenshots-of-i2s-audio-signals

    Then also take a screenshot of the audio waveform. 1kHz sine wave would be good. This can sometimes give a clue as to what is going on. 

    There also can be clocking issues. Detail your clocking system and what sampling rate you are using. 

    Thanks,

    Dave T

  • Hi Dave,

    Thanks for getting back to me so quickly.

    Here's the TDM8 screenshots:

    1: FS, 2: PCM (DSDATA1)

    1: FS, 2: BCLK

    1: FS, 2: BCLK (Zoomed out).

    So as per the scope the TDM8 looks to be correct.

    Note, this is playing 8CH sine wave (sine wave is identical in each channel).

    The Sample Rate is 48kHz.

    The input audio is 16-bit, but the audio was leaking into other channels because the DAC is expecting 24-bit. So I changed the DacBuffer to 24-bit and modified the function which copies from the UsbBuffer to the DacBuffer and now the channels are correct and don't leak into each other as before.

    What specifically do you need to see with respect to the clocking system?

    In the file usbd_audio_drv_adau1979.h (Note, Config settings for ADAU1962A here...) configuration is as follows:

    /* DAC Master clock frequency */

    #define ADAU1962A_MCLK_IN (24576000u)

    /* DAC sample rate */
    #define SAMPLE_RATE (48000u)

    /* ADAU1962A SPORT config parameters */
    #define LR_B_CLK_MASTER_1962 (true)
    #define BCLK_RISING_1962 (true)

    #ifdef TDM_MODE
    #define LRCLK_HI_LO_1962 (false)
    #else
    #define LRCLK_HI_LO_1962 (true)
    #endif

    In File usbd_audio_drv_adau1979.c the following is modified:

    uint32_t adi_codec_Adau1962aInit(ADI_ADAU1962A_HANDLE *pHandle, ADI_CALLBACK pfCallback)
    {
    ADI_ADAU1962A_RESULT eResult;
    ADI_ADAU1962A_TWI_CONFIG TwiConfig;
    ADI_ADAU1962A_SPORT_CONFIG SportConfig;

    /* Open ADAU1962A device instance */
    if((eResult = adi_adau1962a_Open(ADI_CODEC_DEVICE_NUM,
    ADI_ADAU1962A_SERIAL_MODE_TDM8,
    &Adau1962aMemory,
    ADI_ADAU1962A_MEMORY_SIZE,
    pHandle)) != ADI_ADAU1962A_SUCCESS)
    {
    printf ("ADAU1962A: Failed to open ADAU1962A device instance, Error Code: 0x%08X\n", eResult);
    /* return error */
    return 1u;
    }

    /* TWI parameters required to open/configure TWI */
    TwiConfig.TwiDevNum = ADI_CODEC_TWI_DEVICE_NUM;
    TwiConfig.eTwiAddr = ADI_ADAU1962A_TWI_ADDR_04;
    TwiConfig.TwiDevMemSize = ADI_TWI_MEMORY_SIZE;
    TwiConfig.pTwiDevMem = &TwiMemory;

    /* Configure TWI */
    if ((eResult = adi_adau1962a_ConfigTwi (*pHandle, &TwiConfig)) != ADI_ADAU1962A_SUCCESS)
    {
    printf ("ADAU1962A: Failed to configure TWI, Error Code: 0x%08X\n", eResult);
    /* return error */
    return 1u;
    }

    /* SPORT parameters required to open/configure SPORT */
    SportConfig.SportDevNum = ADI_CODEC_SPORT_DEVICE_NUM;
    SportConfig.eSportChnl = ADI_ADAU1962A_SPORT_B;
    SportConfig.eSportPri = ADI_ADAU1962A_SERIAL_PORT_DSDATA1;
    SportConfig.eSportSec = ADI_ADAU1962A_SERIAL_PORT_NONE;

    SportConfig.SportDevMemSize = ADI_SPORT_DMA_MEMORY_SIZE;
    SportConfig.pSportDevMem = &Adau1962aSportMemory;

    /* Configure SPORT */
    if ((eResult = adi_adau1962a_ConfigSport (*pHandle, &SportConfig)) != ADI_ADAU1962A_SUCCESS)
    {
    printf ("ADAU1962A: Failed to configure SPORT, Error Code: 0x%08X\n", eResult);
    /* return error */
    return 1u;
    }

    /* DAC Master Power-up */
    if ((eResult = adi_adau1962a_ConfigDacPwr (*pHandle,
    ADI_ADAU1962A_CHNL_DAC_MSTR,
    ADI_ADAU1962A_DAC_PWR_LOW,
    true)) != ADI_ADAU1962A_SUCCESS)
    {
    printf ("ADAU1962A: Failed to configure DAC power, Error Code: 0x%08X\n", eResult);
    /* return error */
    return 1u;
    }

    /*
    * Configure PLL clock - DAC is clock master and drives SPORT clk and FS
    * MCLK 24.576 MHz and PLL uses MCLK
    */
    if ((eResult = adi_adau1962a_ConfigPllClk (*pHandle,
    ADAU1962A_MCLK_IN,
    ADI_ADAU1962A_MCLK_SEL_PLL,
    ADI_ADAU1962A_PLL_IN_MCLKI_XTALI)) != ADI_ADAU1962A_SUCCESS)
    {
    printf ("ADAU1962A: Failed to configure PLL clock, Error Code: 0x%08X\n", eResult);
    /* return error */
    return 1u;
    }

    /*
    * Configure serial data clock
    * DAC as clock master, External BCLK, Latch on raising edge
    * LRCLK at 50% duty cycle, MSB first, Left channel at LRCLK low
    */
    if ((eResult = adi_adau1962a_ConfigSerialClk (*pHandle,
    LR_B_CLK_MASTER_1962,
    false,
    BCLK_RISING_1962,
    /* pulse mode - true */
    true, //TDM Mode = true Else false
    false,
    LRCLK_HI_LO_1962)) != ADI_ADAU1962A_SUCCESS)
    {
    printf ("ADAU1962A: Failed to configure serial data clock, Error Code: 0x%08X\n", eResult);
    /* return error */
    return 1u;
    }

    /* Power-up PLL */
    if ((eResult = adi_adau1962a_ConfigBlockPwr (*pHandle,
    false,
    true,
    true)) != ADI_ADAU1962A_SUCCESS)
    {
    printf ("ADAU1962A: Failed to Power-up PLL, Error Code: 0x%08X\n", eResult);
    /* return error */
    return 1u;
    }

    /* Configure Sample rate */
    if ((eResult = adi_adau1962a_SetSampleRate (*pHandle, SAMPLE_RATE)) != ADI_ADAU1962A_SUCCESS)
    {
    printf ("ADAU1962A: Failed to configure Sample rate, Error Code: 0x%08X\n", eResult);
    /* return error */
    return 1u;
    }

    /* Configure Word width */
    if ((eResult = adi_adau1962a_SetWordWidth (*pHandle,
    ADI_ADAU1962A_WORD_WIDTH_24)) != ADI_ADAU1962A_SUCCESS)
    {
    printf ("ADAU1962A: Failed to configure word width, Error Code: 0x%08X\n", eResult);
    /* return error */
    return 1u;
    }

    /* Register callback */
    if ((eResult = adi_adau1962a_RegisterCallback (*pHandle,
    pfCallback,
    NULL)) != ADI_ADAU1962A_SUCCESS)
    {
    printf ("ADAU1962A: Failed to register callback, Error Code: 0x%08X\n", eResult);
    /* return error */
    return 1u;
    }

    return 0u;
    }

    The rest of the setup (config) is as the example project defines by default, I know there's something else I'm missing as the audio is tinny, but as far as I can tell the settings that make the ADC_DAC Example project work with TDM8 are all transferred into the USB project.

    Note, I have also setup the SPORT2B to mimic the ADC_DAC project - another thing I did when trying to get the audio correctly out of each channel.

    Any advice you can offer is greatly appreciated.

    Thanks in advance,

    Andrew.

  • 0
    •  Analog Employees 
    on May 2, 2019 2:43 PM in reply to andy@sr

    Hello Andrew,

    Remember that I am not the SHARC support person. For me the code does not help me too much. I am not certain what is actually being executed since I have no way to know if some of the statements are true or false. 

    It looks like you have a 24.576MHZ master clock.

    It looks like the DAC is a master. 

    I see in one place that the LRCLK is set to 50/50 and in another to pulse mode. 

    So what would be handy is to know what the actual register settings are on the DAC?

    The screenshots are helpful. You missed the detail about not using a single sweep but to set the persistence on and to take a screen capture rather than a single sweep. Then you see all the bit transitions and you do not miss  the MSB. However, it looks like you did capture a negative number so that the MSB is high. 

    That screenshot tells me that you are sending the audio data left justified. Often with TDM the data is delayed by one bit clock cycle so we need to be certain that the DAC is set the same way. If it is not then you will miss the sign bit and I think that audio will sound horrible. On a scope it looks terrible. 

    Now your bitclock waveform. The good news is that there is no overshoot or undershoot! That is good, but there is a lot of high frequency roll-off. It will degrade your timing margin. Then by having the DAC be the master you degrade the timing margin further because the sending device, the DSP, has to wait for the bit clock edge then once it sees it then it will output the next bit and that takes time. tSODS is usually what it is called in the timing diagrams. 

    So if you start having issues with bit errors, clicks/pops, etc., then you may want to rethink your clocking.

    The SDATA looks a little different. It has a slight over and undershoot so this gives me a hint that the BCLK, LRCLK and SDATA are not treated the same with respect to the transmission lines on the PCB. I think you are using one of our evaluation boards... When it comes time to build your own boards I suggest you treat these signals the same because the timing of the edges are very important.  

    So send over a register setting list. The hex values. If it is just the registers that are changed that is fine, I will assume all others are at the default settings.  Then I will check to see if you have the DAC set properly. 

    Thanks,

    Dave T

  • Hi Dave,

    I am attaching the register setting list, I think this is what you require, if not, please advise?

    In addition, can you please highlight where the  LRCLK is set to 50/50?

     

    Many Thanks,

    Andrew

  • 0
    •  Analog Employees 
    on May 2, 2019 5:25 PM in reply to andy@sr

    Hello Andrew,

    These are SHARC register settings. I am only concerned with the DAC. I support the DAC and wrote that datasheet. I hope someone else from the SHARC DSP support group will look into the other settings and questions you have. 

    The LRCLK is set with the DAC Control Register 1 located at address 0x07 and bit 6 will set it to pulse or 50/50% duty cycle. 

    Here is your code segment that suggests that it could be set to 50/50. This is what I mean that I have no idea what is actually being executed. 

    * Configure serial data clock
    * DAC as clock master, External BCLK, Latch on raising edge
    * LRCLK at 50% duty cycle, MSB first, Left channel at LRCLK low
    */
    if ((eResult = adi_adau1962a_ConfigSerialClk (*pHandle,
    LR_B_CLK_MASTER_1962,
    false,
    BCLK_RISING_1962,
    /* pulse mode - true */
    true, //TDM Mode = true Else false
    false,
    LRCLK_HI_LO_1962)) != ADI_ADAU1962A_SUCCESS)
    {

    I am just trying to be certain you are setting the DAC to the correct setting for the format of the data you are sending and that you are setting the PLL correctly etc. The fact that you are hearing some audio means you are probably not far off. 

    So send me the DAC register settings that are being sent to the DAC. Another thing you could do is to read back all the registers after configuring to see what they are actually set to. 

    Thanks,

    Dave T