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CrossCore Embedded Studio vs. VisualDSP++ Compiler Efficiency

Just wondering, does VisualDSP++ and CrossCode have same compiler efficiency ? (or i miss some compiler options to enable)

Same code for VisualDSP++ runs at 900KHz  but compiled on CrossCode with same optimization runs just over 530KHz. Also VisualDSP++ code runs with no glitches, but CrossCode have some strange behavior

     int i = 0;

    asm("bit set FLAGS FLG1O;");

    asm("bit set FLAGS FLG0O;");

    while(i<128)

    {

        sinusas[i]=sinf(0.4908738521f*i);

        cosinus[i]=cosf(0.4908738521f*i);

        i++;

    }

    i=0;

    while(i<256)

    {

        adc[i]=(int)(32767.0f+32765.0f*cosf(0.4908738521f*i));

        i++;

    }

    while(1)

    {

        i=0;

        real = imag = 0;

        while(i<128)

        {

            real+=adc[i+offset]*cosinus[i];

            imag-=adc[i+offset]*sinusas[i];

            i++;

        }

        if(Faze(imag,real)>0)

        {

            asm("bit clr FLAGS FLG0;");

        }

        else

        {

            asm("bit set FLAGS FLG0;");

        }

        asm("bit tgl FLAGS FLG1;");

        if(offset>13)

            offset=0;

        else

            offset++;

    }

This should give square wave in FLG0 because of linear phase shift (made by offset, it gives 2pi phase shift) in single point DFT calculation, but it produces many glitches

  • The compiled code should be similar if not better using CCES compared to VisualDSP++. It's hard to be sure what the issue is without a way of running the code so we can debug it. Could you maybe email your project and instructions for reproducing the issues you are seeing to processor.tools.support@analog.com with a link to this forum thread?

    One point to mention that might be relevant is that the default for SIMD code generation has changed. The SHARC compiler no longer issues SIMD code by default as it did in VisualDSP++ 5.0. To enable SIMD code generation in CCES you can use the following compiler switches:

     

    -asms-safe-in-simd-for-loops

    Instructs the compiler that inline asm() statements inside loops

    marked with the SIMD_for pragma are safe to run unchanged in

    SIMD mode.

    -linear-simd

    Instructs the compiler to look for opportunities to use SIMD

    mode for parallel computations in linear code.

    -loop-simd

    Enables automatic use of SIMD mode in loops, aggregate

    assignments and inlined memcpy operations by asserting that data

    buffers are safe to access in this mode.

    Regards,

    Stuart.

  • Hi Kilohercas,

    When replying to a post, you can use the 'Use advanced editor' link in the top-right of the reply box to go to the advanced editor, where it is possible to add attachments. In cases like this - where the issue may be one of differently configured Project Options, it is beneficial to be able to have the complete project so that we can be sure we are building with the same project options to reproduce the performance you are seeing, and advise where changes can be made.

    Regards,

    Craig.

  • you need to check with oscilloscope flag  FLG0; when compiled with different compilers.
    VisualDSP++ will give square wave (as it should do), but CrosCore will give lot if glitches . FLG1 will give speed of loop (since it's toggle, that means 2x faster than frequency of FLG1 itself)
    Since i don't have any debugger i can't tell more

    attachments.zip