ADSP-SC8xx FAQs

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8-Bit DDR Link Port Data Transfer at 125 MHz

Question: Example code for testing 8-Bit DDR Link Port on the ADSp-21835 Eval board Answer: "The attached example project demonstrates 8-bit DDR data transfer using the Link Port operating at 125 MHz…
Cycle Count Measurement on ADSP-SC835 processor

Question: How to measure cycle counts on ADSP-SC835 processor Answer: On SHARC+, cycle counts can be obtained by reading the EMUCLK and EMUCLK2 registers. For SHARC-FX, the corresponding register is…
Disable -funsafe-math optimization in Xtensa

Question: How to explicitly disable -funsafe-math optimization in Xtensa Answer: The -O3 optimization level builds upon all optimizations provided by -O2, while applying more aggressive optimization…
Map specific source file to L2 Memory in SC83x

Question: How can a bundle of specific ally named source file s be mapped to a designated section in L2 memory , and how can this be modified in a *.ld linker script? Answer: Mapping a group of source…
TWI Loopback Example for ADSP-SC835

Question: TWI Loopback Example code for ADSP-SC835 Answer: The attached example project which demonstrates an external loopback between TWI1 and TWI2. In this setup, TWI1 is configured as the transmitter…

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