Implementing Safeload Writes on the ADAU1701

In order to use the safeload write feature on the ADAU1701 (also ADAU1702, ADAU1401, and ADAU1401A), a very specific sequence of write commands must be executed. The write sequence is as follows:

  • Safeload Data 0, address 0x0810
  • Safeload Address 0, address 0x0815
  • (optional) Safeload Data 1, address 0x0811
  • (optional) Safeload Address 1, address 0x0816
  • (optional) Safeload Data 2, address 0x0812
  • (optional) Safeload Address 2, address 0x0817
  • (optional) Safeload Data 3, address 0x0813
  • (optional) Safeload Address 3, address 0x0818
  • (optional) Safeload Data 4, address 0x0814
  • (optional) Safeload Address 4, address 0x0819
  • Initiate safeload transfer bit, address 0x081C

Up to 5 target addresses may be written. The writes marked "optional" in the list above only need to be included if more than one parameter is being updated.

The format for the Safeload Address and Safeload Data registers is as follows (from the ADAU1701 datasheet):

A simple example of using the Safeload Data 0, Safeload Address 0, and IST (initiate safeload transfer bit) to set a volume control to 0 dB in parameter memory is shown below. In this example, the target address in parameter RAM is 0x0000. Since only one parameter is being updated, the Data 1, Data 2, Data 3, Data 4, Address 1, Address 2, Address 3, and Address 4 registers may be ignored.

//Write 0x00800000 to set volume to 0 dB
08 10 00 00 80 00 00     //Data 0
08 15 00 00              //Address 0
08 1C 00 3C              //Set IST High

In the case where multiple parameters need to be updated, the additional parameter data and address registers may be used. The following example shows the 5 parameters of an IIR filter being updated.

//Write 1kHz, +5 dB peaking filter coefficients
08 10 00 00 83 57 7E     //Data 0
08 15 00 00              //Address 0
08 11 00 FF 0A B4 47     //Data 1
08 16 00 01              //Address 1
08 12 00 00 74 12 18     //Data 2
08 17 00 02              //Address 2
08 13 00 00 F5 4B B9     //Data 3
08 18 00 03              //Address 3
08 14 00 FF 88 96 6B     //Data 4
08 19 00 04              //Address 4
08 1C 00 3C              //Set IST High

Only one safeload write operation should be attempted per each audio frame.

Comments
Anonymous
  • over 6 years ago in reply to Yagami

    I wonder if it's possible to write to safeload address registers and safeload data registers in a burst mode (address of the first safeload address/data register and then up to 5 parameter addresses or datasets).

    It would save significant amount of bytes written in my case. 

  • over 6 years ago in reply to genp

    Hi genp,

    You can always write these values directly to parameter RAM, bypassing the need for safeload entirely. The only problem is that if you are unlucky and end up writing to a parameter at the exact moment it's being updated by the control port, there might be an audible artifact on the output. That's the problem Safeload was originally designed to solve.

    However, for the sake of speed, you could possibly write to memory directly, if you're OK with the tradeoff of possibly having audible artifacts.

    It might be worth testing just to see how bad it is. Maybe it's not even noticeable!

  • over 6 years ago in reply to Yagami

    Hi Yagami,

    unfortunately, you are absolutely right.

    In a current project for sound development I need to update 6 input levels on 4 mixers every 10 mS.

    It's 24 levels with 3 writes for each updates = 72 writes.

    In the previous project (on 1442) I had 22 12-input mixers, but was able to use DMA due to

    sequential writes.

     

  • over 6 years ago in reply to genp

    Hi Gennady,

    I may be wrong, but I think you're only able to do the trick where you keep the chip select line low throughout the duration of the writes when you are writing to contiguous (sequential) addresses in memory. Since your target addresses 0x0810, 0x0815, and 0x081C are not sequential, I imagine that you need to bring the chip select line high between each of the three writes.

  • over 6 years ago

    Another clarification required, please.

    Some details are skipped in this otherwise great description.

    I am using SPI port for communication.

    According to the datasheet, every message requires first byte 0x00 (in my case) of device address and Write.

    So do I need to latch every message like this (the above single write is used as an example):

    CS LOW

    00 08 10 00 00 80 00 00     //Data 0

    CS HIGH

    CS LOW
    00 08 15 00 00              //Address 0

    CS HIGH

    CS LOW
    00 08 1C 00 3C              //Set IST High

    CS HIGH

    or do I latch the whole packet:

    CS LOW

    00 08 10 00 00 80 00 00     //Data 0

    00 08 15 00 00              //Address 0

    00 08 1C 00 3C              //Set IST High

    CS HIGH


    I remember that when using 1442 I used DMA for safeload write, so I did latch the whole packet.

    On 1701 it doesn't seem to work, or I am doing something wrong.

    Thank you,

    Gennady

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