I have designed a board with couple of ADAV400 and AD1702 DSPs, and AD1974 ADCs. DSPs are clocked with 64 * fs (3.072 MHz) and ADC generate iternal clock from LRCLK. PLL filters of all chips are made according to their datasheets. For ADAV400 is 2 kohm + 100 nF and 1 nF in parallel. As result ADAV400 DSPs are very sensitive to noise. Touching the PLL componets for ADAV400 cause it to produce only a noise, while same test on AD1702 and AD1974 doesn't change their work.
Are PLL filter components depends on MCLKI frequency? Is it possible to be optimized for better resuts for a given clock rate?