ADAV400 PLL filter components

Hello.

I have designed a board with couple of ADAV400 and AD1702 DSPs, and AD1974 ADCs. DSPs are clocked with 64 * fs (3.072 MHz) and ADC generate iternal clock from LRCLK. PLL filters of all chips are made according to their datasheets. For ADAV400 is 2 kohm + 100 nF and 1 nF in parallel. As result ADAV400 DSPs are very sensitive to noise. Touching the PLL componets for ADAV400 cause it to produce only a noise, while same test on AD1702 and AD1974 doesn't change their work.

Are PLL filter components depends on MCLKI frequency? Is it possible to be optimized for better resuts for a given clock rate?

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  • 0
    •  Analog Employees 
    on Feb 10, 2010 10:21 PM

    The PLL filter components do not need to change based upon your input clock. It's likely that this noise issue may be related to the board layout. Have you kept the filter components close to the pin, without long traces between any of the components and/or the filter pin on the ADAV400? Could you post an image of your layout here so that we can see how the components look on your board?

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  • 0
    •  Analog Employees 
    on Feb 10, 2010 10:21 PM

    The PLL filter components do not need to change based upon your input clock. It's likely that this noise issue may be related to the board layout. Have you kept the filter components close to the pin, without long traces between any of the components and/or the filter pin on the ADAV400? Could you post an image of your layout here so that we can see how the components look on your board?

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