ADAU1446 CLKOUT modulating

Hi. I've built a prototype using the ADAU1446 using the CLKOUT as fs*256 to clock a CODEC. It's working and I'm not conscious of any problems with the output signals that might be caused by the master clock. However, CLKOUT appears to be frequency modulating at about 24kHz (fs=48kHz), the oscillator itself is stable. As best as I can tell fs is also stable. Any ideas? Is this something I'm likely to see using the fs*256 option? Would I be better using the buffered oscillator? tia Gordon

  • Error. It's modulating at 48kHz. I was looking for when it came back in sync but missed the first 'node'.

    Gordon

  • 0
    •  Analog Employees 
    on Feb 27, 2010 2:11 AM

    Hello Gordon,

    We haven't seen this kind of behavior on the evalution board of the ADAU1446. In order to provide you with further assistance, we'll need some more detailed information about your application and setup.

    1 - Please provide your SigmaStudio project file. If you're concerned about showing your signal flow to the public, then you can simply delete all of the cells from the schematic tab. The only information I'm really concerned about is the register settings.

    2 - Please provide a schematic or basic description of the hardware, specifically the interconnection of the ADAU1446 and the codec.

    3 - Please provide any scope shots that might help us to better understand the issue.

    Best Regards,

    Brett

  • Hi Brett. Thanks for the response. You've given me some pointers so I'll cut a few tracks and pull a few R's before troubling you further. I'll post back if I can narrow the problem down a bit.

    I'll try and get some scope shots anyway but it might not be very informative. I check it by setting the A time base to 0.5us then increasing the delay on the delayed trace set at 0.05us. As you increase the delay you see what looks like jitter but as it approaches ~4.2 the 'jitter' disappears. Increase the delay further and the 'jitter' comes back to disappear again at ~8.4. So what you see depends on the delay position.

    Doesn't do it until it's been compiled if it helps. I've had the circuit right down to a minimal setup so don't /think/  it's down to the circuit itself. I'll have another basic circuit test tomorrow.

    Cheers

    Gordon

  • Hi Brett. Disconnected everything from the CODEC, no change. If I reduce the schematic to it's bare minimum, the 'jitter' reduces. I can't get a decent scope shot, sorry. Project file attached. There isn't really much to the circuit once the codec's disconnected. It's running at the default 48k with component values for PLL as per ADAU1446 spec sheet. CLKOUT as I've said is running at 256*fs, CLKMODE0=LOW, CLKMODE1=HI. RSVD and RST tied low. SPDIFO is driving one of these http://tinyurl.com/y8uj6rz. SDATA_IN0 is the only input. MP10 has a 10k pullup. All other MP pins are open as they go out to a header which isn't plugged in. CLATCH is tied to ground. It's a two layer board and all chip power pins are decoupled as close as I could manage to the chip. No uP, just an EEPROM which is working/self booting OK. The crystal is the same one used on the ADAU1701 evaluation board. Remember, it only 'jitters' once it's been compiled.

    Won't expect to hear from you before Monday.

    Have a good weekend.

    Gordon

    1446-Modulation.dspproj.zip
  • 0
    •  Analog Employees 
    on Mar 1, 2010 8:21 PM

    Gordon wrote:

    RSVD and RST tied low.


    The Reset pin is active low, so if this is true, you are essentially holding the chip in reset/standby mode. Is this correct, or a typo?