Several questions about ADAU1442

Hello,

I have a few questions about the ADAU1442:

1. Do any of the following pins have pullup resistors:

ADDR0
ADDR1
SELFBOOT
CLKMODE0
CLKMODE1
PLL0
PLL1
PLL2
RESET

When I look at the evaluation board schematics ( www.analog.com/static/imported-files/user_guides/UG-032.pdf )
I'm pretty sure that all the pins except RESET have internal pullups because a dipswitch is used to connect them to ground, however this is not decribed in the datasheet and i would like to know for sure.

2. is the output of the external clock (in buffered oscillator configuration) dependent of the state of the reset pin?
i.e. is there still an external clock when the oscillator is running and the reset pin is pulled low?

3. When using a serial output port in slave mode, what happens when data is not clocked out within time? How does the master on the other side knows that the SigmaDSP is ready to start sending the audio stream?

4. When I look at Table 20. Master Mode Clock Domain Assignment on page 34 of the datasheet and compare it with the pinout i notice the following:
The BCLK, LRCLK and SDATA_IN pins are next to each other in each pair. However all the SDATA_OUT pins are seperated from the respective BCLK and LRCLK pins.

For example take clock domain 1, an exclusive input port:
LRCLK1: pin 10
BCLK1: pin 9
SATA_IN1: pin 8

Clock domain 4 set as input port:
LRCLK4 : pin 97
BCLK4    pin 96
SDATA_IN4: pin 95

Clock domain 4 set as output port:
LRCLK4 : pin 97
BCLK4    pin 96
SDATA_IN4: pin 79

Clock domain 9, an exclusive output port:
LRCLK9: pin 71
BCLK9: pin 70
SATA_OUT0: pin 98

Are my observations correct? This would mean that output ports are less easy to route on a PCB.

5. How to put the SigmaDSP in SPI mode? There are several references in the datasheet to SPI mode however it is not explained how to actually put the device in SPI mode.

6. The evaluation board uses a ADM811 to generate the reset signal. This chip has a minimum reset delay of 140ms after the power supply is within specifications. Is such a long delay neccesary? Do we have to wait till the PLL has locked before pulling up the reset? In that case how do we know that the PLL has locked other than using a large enough delay to be safe? The minimum PLL lock time is not specified in the datasheet as far as i can see.

  • 0
    •  Analog Employees 
    on Feb 3, 2011 7:45 PM over 10 years ago

    1.

    I am confirming this with the chip designers.

    2.
    In 256 × fS,NORMAL mode or 512 × fS,NORMAL mode, CLKOUT will be disabled when the reset line is held low.
    However, in buffered oscillator mode, CLKOUT will be active at all times, even when reset is held low.

    3.
    Every time the core completes processing a sample, it outputs it to the serial port buffer. This data will be output by the serial port until the next frame is completed. If your external device does not clock the serial port at this time, that data will simply be "lost."
    In theory, the external device driving the serial port should be synchronous to the core, so it should constantly be clocking the serial port and will receive one sample of data per channel per frame as long as the clocks continue.
    If your external device is asynchronous to the core, you'll need to route the audio data through the ASRCs, which need to be receiving their clocks from the slave serial port. In the same way, the ASRC should generate one new sample per frame (as received on the slave serial port's LRCLK).
    In other words, data will always be available as long as the master is sending clocks the the ADAU1442.

    4.
    Your understanding is correct. The pin placement of the serial output ports and respective clocks is a little illogical and makes it difficult to route the serial outputs on a PCB. We've learned from this mistake and are attempting to make a more logical pin-out on our new SigmaDSPs in development.

    5.
    In the datasheet, Rev. C, page 26, the Control Port description states: "When the SELFBOOT pin is low at power-up, the chip defaults to I2C mode but can be put into SPI control mode by pulling Pin CLATCH low three times." This basically means that you need to toggle the SPI latch line 3 times and the chip will change over to SPI mode. These toggles can be as slow as you want (or as fast as an MCLK cycle). Most system designers implement this function as 3 "dummy writes" (i.e. SPI writes that contain no valid data, simply for the sake of pulling the latch low).

    6.
    The PLL lock time calculation is described in the datasheet, Rev. C, page 20. I have copied that section of the datasheet below for your reference.

  • Hello Brett,

    Thank you for your great answers.

    Some things are still unclear to me, which i hope you can clear up.

    Regarding my question 3: I assume that double buffers are used? i.e one regular buffer and a shift register. Because my master might be start clocking in the frame after a few BCLK time because the two devices are not fully synchronized (however running at the same freq), the master does not know when a frame is set ready at the slave DSP. If there are no double buffers, the data in the shift register will be discarded before it was fully clocked out.

    I would like to add to my question 3: What happens when the master tries to clock in a frame while the DSP is not ready because it is still in initialisation mode or because the settings are wrong? I assume it will receive all zeroes? I think it would be a good idea to connect a GPIO pin from the slave to the master so the slave can notify the master that it is ready to send data.

    About question 6: The PLL locking happens after the reset pin is deasserted (pulled high) so the delay in the reset generator does not have to count in the PLL locking time. One has only to count in the crystal oscillator startup time i assume?

    Thank you kindly,

    Bianco Zandbergen

  • 0
    •  Analog Employees 
    on Feb 17, 2011 11:46 PM over 10 years ago

    Sorry for the delay. I'm still waiting on a response regarding the pull-up / pull-downs.

    3. I'm not sure of the internal circuitry, but I think in this case it doesn't matter. If your external master is clocking the serial port, then the ASRCs will take their target clock rate from the serial ports themselves. In other words, your master isn't only clocking the serial port, it's clocking the ASRC. That way, the ASRC outputs will always be in sync with the serial port, which will in turn be in sync with your master, so there's no need to worry about dropped data. Of course, you need to keep the ASRCs constantly clocked in order to make sure they function properly (in other words, make sure you're not enabling/disabling the master clocks on the serial port during operation).

    6. That's right!

  • 0
    •  Analog Employees 
    on Feb 18, 2011 12:11 AM over 10 years ago

    I just received an answer from the IC designers regarding the internal pull-ups / pull-downs. It turns out that all digital signal pins have both pull-ups and pull-downs internally. The pull-ups are not as weak as maybe they should be... on the order of 20k. So, in order to cut down on leakage current it would still be helpful to have an external pull-up or pull-down if possible.