I’ve implemented a 5 band peaking equalizer using the ADU1701. The ADU1701 interfaces with a microcontroller via SPI. Using the safeload mechanism, updating coefficients of each band works most of the time(approx. 90%). However, there are occasional safeloads that result in unexpected behavior – scrambled sounding audio or no audio output.
After a safeload in which the filter fails, reading back coefficients from parameter ram reveals a mismatch. I’ve only ever detected one out of the five coefficients showing a mismatch with what was sent by the microcontroller, and it is never the same coefficient. Moreover, the mismatch parameter ram value appears to be of the previous filter configuration.
My firmware waits for the IST bit to clear before initiating a safeload.
The last paragraph on page 35 of the ADU1701 datasheet reads:
“When the initiate safeload transfer bit is asserted, only data from those two registers are sent to the RAM; the other three registers are not sent to the RAM and may hold old or invalid data. “
This is precisely what seems to be happening in my application except I’m updating all five coefficients.
Beyond waiting for the IST bit to clear, is there anything more I can do to reach a 100% safeload success rate?
Would writing zeros to the safeload data ram before writing the new coefficients help?
Does it matter which order you update the safeload address / data registers?
Thanks in advance for your help.
Thanks Bob. I'll make an FAQ about this right away. It should definitely be featured more prominently.