AD1940

I am designing a system with a AD1940 controlled off a Pic24F microcontroller.

For testing the hardware, I have a simple 4 in 4 out schematic, no processing, no volume controls.  Straight in straight out.

I a have a 12.288 MHz master clock, with 4 inputs input 48 k 24 bit left justified.

The board is 4 layers and the signal integrity looks good.

I verified I can read and write to the SPI Port. However, after initializing everything, downloading the code, I get nothing on any of the serial outputs.

The only thing I have found odd, is when  read from the DSP Core control Register ( 2642), I get a one in bit 14 which is a reserved bit. The one is also set for bit 9.  If I write a 0x00 to (2642) , when I read it back , there still is a one in bit 14. I can read and write to other registers.

Does anyone know what these reserved bits are for?

So far I can not figure out hat is wrong whether it is software  or hardware.

Does anyonw have any good advice ?

  • 0
    •  Analog Employees 
    on Aug 10, 2011 9:15 PM

    This reserved bit (14) cannot be overwritten, so you can effectively ignore it. You need to write bit 9 as 1 in order for audio to pass through the chip. So, in other words, you should write 0x02 0x00 to the core control register, but if you read it back, you'll read 0x42 0x00 because bit 14 is always set.

    Are your serial output ports in master mode or slave mode. If they are in slave mode, are you supplying proper LRCLK and BCLK signals to the appropriate pins? If they are in master mode, have you set the Serial Output Registers (addresses 0xA54 and 0xA55) properly?

  • Brent,

    After writing the email , I read the register 0x2642 on the Eval unit and I saw the same bit 14 as 1 so I figured that was not the problem.

    The default download setup writes a 1 in bit 9 , which I also verifed was set by reading the it thru the SPi interface.

    I have a Master Clock, LR clk, and block clock, and digtal data appied to the inputs, but get no output. All the clocks, and digtal data looks and is not noisy. 

    I have two prototype boards and both do the same thing thing.

    I am baffled.

  • 0
    •  Analog Employees 
    on Aug 10, 2011 9:53 PM

    Remember, there are several sets of LRCLK and BCLK pins.

    LRCLK_IN, BCLK_IN - these are used to clock data into the serial input ports.

    LRCLK_OUT0, BCLK_OUT0 - these are used to clock data into the serial output ports 0-3.

    LRCLK_OUT1, BCLK_OUT1 - these are used to clock data into the serial output ports 4-7.

    So, that's a total of 6 clock pins. Are you supplying clocks to all of the pins in use? If your serial ports are in slave mode, you'll need to connect at least 2 LRCLK pins and 2 BCLK pins (one pair on the input side and one pair on the output side).

  • Brent,

     

    That may be the problem. I am not supplying LR and BLk clocks to the outputs

    ports and operating in the slave mode.

     

    Does the slave mode only affect the output or does it also affect the

    inputs?  I am using a Codec to supply the Ad1940 with the input digital

    stream,. The Codec also takes the output of the AD1940 to convert it back to

    analog.

    The codec generates the MCLK, the LR Clock and block clock. . If the master

    mode is set o nthe output does it also affect he input?

     

    Rich

  • 0
    •  Analog Employees 
    on Aug 10, 2011 10:38 PM

    The input serial port is always in slave mode, but the output ports can be independently configured as either slave or master. You'll find a checkbox in SigmaStudio's register control GUI that toggles the mode of each output port.