ADAU1701: ADC resistor values for higher sample rates

Hi Steve, and welcome to the forum.

Fortunately, I think I know the exact reason why this is happening! Unfortunately, I think it points out a lack of clarity in our datasheet.

As explained in the datasheet, the series resistors on the ADC inputs only need to be changed "is if a sampling rate other than 48 kHz is used." That being said, the definition of "sample rate" used here is somewhat ambiguous and misleading.

In some types of DSP (or codecs), in order to increase or decrease the sample rate, you simply scale the clock signals accordingly. For example, if you're feeding a 12.288 MHz master clock into the system for a 48 kHz sample rate, then you can simply scale that down by 8.125% to 11.2896 MHz for a 44.1 kHz sample rate, or double it to 24.576 MHz for a 96 kHz sample rate, etc... In many kinds of ICs, you are free to do this (as long as you stay within the boundaries of allowable clock frequencies) and all of the internally generated clocks will simply scale accordingly.

The ADAU1701 is a bit different. The PLL takes in a master clock and divides it down before multiplying it up to a much higher frequency. For a 48 kHz sample rate, the DSP core clock is 1024 * 48000 = 49.152 MHz. Now, when you want to use a 96 kHz sample rate, logically you might assume that the core clock doubles to 98.304 MHz. However, this is not the case for the ADAU1701. Its DSP core clock can only run up to somewhere in the 50 MHz range before things start to break down and function incorrectly. Scaling down for a 44.1 kHz sample rate is not a problem (the DSP core clock can easily run at 44.1584 MHz.

So, an alternate method is used for higher sample rates. For 96 kHz (which we refer to as "double rate" or "dual rate" in some other SigmaDSP datasheets), the DSP core simply grabs a sample twice as often as it did at 48 kHz. This also makes the interpolation and decimation filters for the converters run twice as fast, and has the side effect that the DSP core can only execute half as many samples as it could at the "normal rate" of 48 kHz.

Quad rate is possible as well, using the same method. The DSP core quadruples the rate at which it grabs samples from the converters and serial ports, and the interpolation and decimation filters do the same. Instead of scaling the frequency up or down of all of the clocks in the system, you're simply doubling or quadrupling the clock frequencies for certain subsystems.

That being said, the explanation regarding the ADC resistors refers more to the case I originally described above, where you might be running your system at 44.1 kHz or maybe at some strange non-standard rate like 49 kHz or 42 kHz. In that case, you're literally scaling the frequency of the MCLK, so the ADC resistor values need to scale as well.

Conversely, if you are running at 96 kHz, the MCLK frequency itself remains unchanged, and you're simply doubling the rate of the DSP core and converter filters. In that case, you only need to change a register setting, and no hardware changes are required.

In summary, the ADC_RES values for 48 kHz and 96 kHz should be the same, because the core clock frequencies are the same in both cases.

In retrospect, the datasheet does a poor job of explaining this. I will make this into a FAQ on EngineerZone in order to help clear up any confusion on the subject.

Let me know if you have questions!

Brett

Hi Brett,

Thank you very much for your answer, which makes perfect sense.

So where the datasheet refers to the sample rate in the ADC calculations, it in fact means the "effective sample rate", where:

effective sample rate = actual sample rate (for normal rate systems) or

effective sample rate = actual sample rate/2 (for double-rate systems) or

effective sample rate = actual sample rate/4 (for quad-rate systems)

I feel more comfortable about what I have done now. With the hardware working, tomorrow I can get on with testing the code...this is my first project using the SigmaDSPs and I am excited by the possibilities that they open up.

I hope that making this a FAQ will save others some head-scratching!

Thanks again and kind regards,

Steve L.

Steve, that's exactly right! In fact, some of the newer SigmaDSP datasheets (like the ADAU144x) use that same kind of terminology. In the Master Clock and PLL section of the ADAU144x datasheet, the concepts of fCORE, fS,NORMAL, fS,DUAL, and fS,QUAD are described in detail.

If you have any questions, check out page 20 and 21 of Rev C: http://www.analog.com/static/imported-files/data_sheets/ADAU1442_1445_1446.pdf

This is a similar architecture to that of the ADAU1701.