AD1938 BCLK trouble

Hello to all,

i designed a product with the adau1442 and multiply AD1938 Audio Codecs. In first i transfert all the audio datastream in stereo mode. Now i want to minimise the cable and change the system to work with TDM8 mode. So this is still working at the moment.

I have trouble with generating the BCLK of the ADC internaly. In case of the DAC it works fine.

I'm generating the MCLK with the internal PLL from the LRCLK. So the only Audio-lines i want to connect to the AD1938 should be:

- ADATA

- ALRCLK

- DATA

- DLRCLK

is it possible?

If i switch the ABCLK into the internal mode the ADC Datastream fail. My configuration works only if i connect ABCLK to the AD1938 and switch to external BCLK mode.

The DAC performs his operation in both modes.

Do you have an idea how i could change my configuration to minmise EMI and cable connections?

My configuration is updated at the moment in SigmaStudio 3.1 with USBi interface connected to the ADAU1442(i2c), EEPROM(i2c) and AD1938(SPI)

Thank you very much!

M.Bente

  • 0
    •  Analog Employees 
    on Oct 28, 2011 5:29 PM

    Hi-

    I moved this question to the SigmaDSP Processors community.  Please continue the discussion here.

    Thanks,

    AndyR

    EngineerZone Community Manager

  • 0
    •  Analog Employees 
    on Oct 28, 2011 5:48 PM

    Hi,

    Can you tell me what you are writing to the ADC Control 2 register? Are you setting the ADC_BCLK_M_S bit to be master? If the ADC BCLK is set to be master you should be able to observe a clock on the ABCLK pin.

    Best Rgds

    Alan

  • Hi! Thank you very much! Now it seems to working if i switch the Master Mode on the AD1938 generates a BClk and i can leave the Pin unconnected.

    Is this configuration a recommend safe operating mode? My PCB's are connected via PCB-Conectors.

    Do you have any experience about generating the BCLK AND MCLK with the internal PLL(from LRCLK)?

    In my design it is very helpful to let this Highfrequency Signals be unconnected.

    In my design the loop Filter is dimensioned to the MCLK filter? May i have to change the Filter to the LRCLK filtertyp?

    Thanks! Best regards!

    M. Bente

  • 0
    •  Analog Employees 
    on Nov 11, 2011 11:58 PM

    Hi,

    Yes, if you want to use the LRCLK  as the input to the PLL then you must use the correct PLL loop filter. I'm not sure if i follow what you mean by leaving the BCLK pin unconnected, if the AD1938 is the master then it would need to drive the BCLK and data to the connected device, you couldn't leave BCLK unconnected?

    Best Rgds,

    Alan

  • Hey! Thank you for your answer. Sorry I've taken so long to reply.

    In my proto design i left the BCLK unconnected and set the AD1938 to generate it internal from the PLL, i thougt i could do this. But if its not a recommend operating mode i will leave the BCLK connected.

    I thougt the BCLK can be synchronized from the LRCLK?, so the AD1938 can generate it internally?

    Greets M.Bente