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Clock for Class D Amp

I need to generate a roughly 700kHz clock for a Class-D amplifier in my design. Can I directly drive a clock input from one of the ADAU1701 GPIOs? The SigmaStudio Oscillators seem to limit at 24kHz max, is there another way to generate a higher frequency signal?

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  • You could enable the OUTPUT_BCLK signal on MP11 and feed it into a counter.

    Cheapest implementation would probably be a 74HC163 - clock it with MP11, strap the terminal count line to the parallel load line, and configure the parallel inputs to give a suitable clock divider. With OUTPUT_BCLK set to /8 (6.144MHz), dividing by 8 gives you 768KHz and dividing by 9 gives you 683KHz. If you want more accurate than that, BCLK at /2 (24.576MHz) divided by 35 gives you 702KHz, but that's a bit harder to pull off with cheap 74xx bits.

    I'm using OUTPUT_BCLK in a design to feed 24.576MHz from an ADAU1701 into a pair of ADAU1592s. Couldn't be happier with it.

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  • You could enable the OUTPUT_BCLK signal on MP11 and feed it into a counter.

    Cheapest implementation would probably be a 74HC163 - clock it with MP11, strap the terminal count line to the parallel load line, and configure the parallel inputs to give a suitable clock divider. With OUTPUT_BCLK set to /8 (6.144MHz), dividing by 8 gives you 768KHz and dividing by 9 gives you 683KHz. If you want more accurate than that, BCLK at /2 (24.576MHz) divided by 35 gives you 702KHz, but that's a bit harder to pull off with cheap 74xx bits.

    I'm using OUTPUT_BCLK in a design to feed 24.576MHz from an ADAU1701 into a pair of ADAU1592s. Couldn't be happier with it.

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