Interfacing ADAU1701 with AD1955

Hi:

I am trying to send the I2S output from ADAU1701 acting as master to a DAC board built around the AD1955. Questions:

1. The ADAU1701 datasheet recommends on p18 that MP11 be used to derive MCLK. Now MP11 also serves the purpose of OUTPUT_BCLK when used for I2S. Therefore does this mean that I can connect MCLK and BCLK together?

2. The ADAU1701 operates at 3V3 and AD1955 at 5V. Is the ADG3304 a good choice to perform the voltage level translation between the two at these frequencies?

Thank you - Ram

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  • Thank you for reviewing my spec Brett.

    Meanwhile I have chosen the ADG3308 instead of the ADG3304 because the A-side Input High Voltage (Min) spec for the 3308 is 0.65xVcca as opposed to Vcca-0.4 for the ADG3304. This means that with the ADG3304 the ADAU1701 needs to output 2.9V for it to be recognized as logic 1 by the ADG3304 but only 2.15V for it to be recognized as logic 1 by the ADG3308. In reality the ADAU1701 outputs closer to 2.4V so it should, going by the specs, not work with the ADG3304. Hmmm.

    I will shortly implement a 3V3-5V translation-plus-MCLK-buffering scheme using a ADG3308, and will post the outcome if successful.

    Best - Ram

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  • Thank you for reviewing my spec Brett.

    Meanwhile I have chosen the ADG3308 instead of the ADG3304 because the A-side Input High Voltage (Min) spec for the 3308 is 0.65xVcca as opposed to Vcca-0.4 for the ADG3304. This means that with the ADG3304 the ADAU1701 needs to output 2.9V for it to be recognized as logic 1 by the ADG3304 but only 2.15V for it to be recognized as logic 1 by the ADG3308. In reality the ADAU1701 outputs closer to 2.4V so it should, going by the specs, not work with the ADG3304. Hmmm.

    I will shortly implement a 3V3-5V translation-plus-MCLK-buffering scheme using a ADG3308, and will post the outcome if successful.

    Best - Ram

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