Products Mentioned

ADAU1761 Production
The ADAU1761 is a low power, stereo audio codec with integrated digital audio processing that supports stereo 48 kHz record and playback at 14 mW from...
Datasheet
ADAU1761 on Analog.com

Associated Drivers

ADMP421 Obsolete
Analog Devices has sold its MEMS Microphone product line to InvenSense. Please visit the InvenSense ADMP421 product page for all technical support and...
ADMP421 on Analog.com

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ADAU1761 setup for digital microphone

		
	
				

			

									
					    Frank.D10
					
							


			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Aug 17, 2012 
				
			
			
		
    
		
		                     
				
        		
    
		    
		    		    
		    			
    
			    
    I have setup an ADAU1761 to work with a digital microphone ADMP421. The microphone input signal works fine and I can route it to the serial port or the SigmaDSP processing unit. However, I am still wondering about the following note in the codec manual. At page 66, in the description of the bit INSEL in register R19, it says:
    
 
    "Digital microphone input select. When asserted, the on-chip ADCs are off, BCLK is master at 128 × f_S, and ADC_SDATA is expected to have left and right channels interleaved."
    
 
    What is the meaning of "128 × f_S" for BCLK? 
    
 
    I have setup the codec for a base sampling frequency of 48.0 kHz  and a sampling frequency of 16 kHz (ADC and DAC, DSP and serial port), the serial port is configured for 64 bit clock cycles per frame. At BCLK I measure a clock frequency of 1024 kHz, which is neither 128 * 48 kHz nor 128 * 16 kHz. When I set the serial interface to 128 clock cycles per frame, then there is no more input signal from the microphone (i.e. only a zero signal). 
    
 
    Can anyone resolve this discrepancy?
    
			
    
			
									
		                             
                        

    
    
                                            
                 Audio Signal Processors
                
                                                    
                 digital_microphone
                
                                                    
                 admp421
                
                                                    
                 SigmaDSP Audio Processors
                
                                                    
                 adau1761
                
                                
            
    
    
    
		
    

				
				        
        		
    
			
						
									
												
			
			
                        
                                    
                        
                        
                        
            
			            
						
						
			
			
			
			
		
    

        
        
        
    
					
    
			
    


    
















    
	
    
	
    
					



			


				
	









	
      
	

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      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Aug 20, 2012 6:23 PM
            
            
						
			            		
      
		
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      The ADAU1761 datasheet generally refers to "Fs" as being the standard audio sample rate of 48 kHz, which is derived from the input master clock using the PLL. That "Fs" can be varied a bit up or down, for example, to 44.1 kHz, in which case all of the associated clock rates on the converters and the serial ports would scale accordingly.
      
 
      The ability to set the converters or the serial port to different sample rates is achieved by simply using a clock divided version of the internal "Fs" clock. For example, you could set the serial port to run at 24 kHz instead of 48 kHz by setting it to use the "Fs/2" clock.
      
 
      In any case, the ADMP421 can only accept a certain range of bit clock inputs. From the datasheet... the input clock period must be between 310 ns and 1000 ns.
      
 
      https://ez.analog.com/cfs-file/__key/communityserver-discussions-components-files/396/b73c42ddc5caa101d1356379ca3d55e5.html
      
 
      If you take the inverse of those clock periods, you can derive that the frequency of the BCLK signal input to the ADMP421 must be between 1 MHz and 3.22581 MHz. In that case, if you are running the ADAU1761 at a sample rate of 16 kHz, then you must select a "BCLK Cycles Per Frame" setting that puts the BCLK signal in the right range for the ADMP421.
      
 
      There are four possible choices:
      
 
      48, 64, 128, 256
      
 
      48 x 16 kHz = 768 kHz. (not acceptable)
      
 
      64 x 16 kHz = 1.024 MHz (OK)
      
 
      128 x 16 kHz = 2.048 MHz (OK)
      
 
      256 x 16 kHz = 4.096 MHz (not acceptable)
      
 
      So, it looks like you have two options: 64x or 128x mode.
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
				
						
						
				
				
		
		
      
			
		
      
	
      

      

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