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Interfacing ADAU1761 x2


I've been working with a pair of 1761 eval boards and have run into a mysterious clock sync problem. Every ~4 seconds I have a short amplitude reduction in the output signal. I'm hearing this as a very brief drop out or click in my headphones. Perhaps I've missed a register setting. The audio streams are otherwise working/sounding fine and I'm running them through a pair of the ADI beamforming algorithms.


Passing a digital signal from the slave board to clock master. I've tried Left/Right Justified and TDM modes, following the configuration parameters from pg 42-43 in the ADAU1761 datasheet.

I've taken a look at this tutorial:

Jumper configuration for my setup is consistent for clock sync and passing ADC to DAC pins. I've not had any luck setting MCLK to the I2S setting, both boards are set to OSC.

Any ideas?



  • Hi Coleman,

    Thank you for continuing to followup on this thread! The source board was causing the trouble as you had suggested. Thankfully we have a few extras available to work with here.

    To summarize:

    I connected switch side of R47 (Master) to EXT_MCLK (Slave) input pin, while making sure EXT_MCLK ground pin of both boards is connected. Master board passed signal from ADC pin to Slave DAC pin. Via Sigma Studio, Master board sends the Microphone signal to DIG0 and DIG1 outputs and presents it to the input block on the Slave board (channel 2/3).

    Resolution - 4 channel beamforming program is working just fine using two 1761 eval boards.



  • Excellent news! Please let us know if have any other questions.