Post Go back to editing

Interfacing ADAU1761 x2

Hello,

I've been working with a pair of 1761 eval boards and have run into a mysterious clock sync problem. Every ~4 seconds I have a short amplitude reduction in the output signal. I'm hearing this as a very brief drop out or click in my headphones. Perhaps I've missed a register setting. The audio streams are otherwise working/sounding fine and I'm running them through a pair of the ADI beamforming algorithms.

Setup:

Passing a digital signal from the slave board to clock master. I've tried Left/Right Justified and TDM modes, following the configuration parameters from pg 42-43 in the ADAU1761 datasheet.

I've taken a look at this tutorial: http://ez.analog.com/message/5675#5675

Jumper configuration for my setup is consistent for clock sync and passing ADC to DAC pins. I've not had any luck setting MCLK to the I2S setting, both boards are set to OSC.

Any ideas?

Best,

John

Parents
  • Thank for you quick the responses Brett and Natan!

    I've tried connecting a wire from R47 on master board to EXT_MCLK pin 10 of slave board and still no result. I had our technician solder the leads so it should be a solid connection. When looking at meters in Sigma Studio I see no signal is passing from the ADC's. Any other steps to try?

Reply
  • Thank for you quick the responses Brett and Natan!

    I've tried connecting a wire from R47 on master board to EXT_MCLK pin 10 of slave board and still no result. I had our technician solder the leads so it should be a solid connection. When looking at meters in Sigma Studio I see no signal is passing from the ADC's. Any other steps to try?

Children
No Data