Post Go back to editing

Interfacing ADAU1761 x2

Hello,

I've been working with a pair of 1761 eval boards and have run into a mysterious clock sync problem. Every ~4 seconds I have a short amplitude reduction in the output signal. I'm hearing this as a very brief drop out or click in my headphones. Perhaps I've missed a register setting. The audio streams are otherwise working/sounding fine and I'm running them through a pair of the ADI beamforming algorithms.

Setup:

Passing a digital signal from the slave board to clock master. I've tried Left/Right Justified and TDM modes, following the configuration parameters from pg 42-43 in the ADAU1761 datasheet.

I've taken a look at this tutorial: http://ez.analog.com/message/5675#5675

Jumper configuration for my setup is consistent for clock sync and passing ADC to DAC pins. I've not had any luck setting MCLK to the I2S setting, both boards are set to OSC.

Any ideas?

Best,

John

Parents
  • You want to have both chips running off the same MCLK signal.  On the board you have designated the slave make sure you have the MCLK source selected as I2S, this would be S5 in the middle position.  I could be wrong about this but I don't think there is a header that will give you the raw MCLK running to your master to bring over to your slave so you will need to solder a wire for the next step.  Solder a wire from the master oscillator (R47) and connect it to the EXT_MCLK input on your slave board (J6-10).

Reply
  • You want to have both chips running off the same MCLK signal.  On the board you have designated the slave make sure you have the MCLK source selected as I2S, this would be S5 in the middle position.  I could be wrong about this but I don't think there is a header that will give you the raw MCLK running to your master to bring over to your slave so you will need to solder a wire for the next step.  Solder a wire from the master oscillator (R47) and connect it to the EXT_MCLK input on your slave board (J6-10).

Children
No Data