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Interfacing ADAU1761 x2

Hello,

I've been working with a pair of 1761 eval boards and have run into a mysterious clock sync problem. Every ~4 seconds I have a short amplitude reduction in the output signal. I'm hearing this as a very brief drop out or click in my headphones. Perhaps I've missed a register setting. The audio streams are otherwise working/sounding fine and I'm running them through a pair of the ADI beamforming algorithms.

Setup:

Passing a digital signal from the slave board to clock master. I've tried Left/Right Justified and TDM modes, following the configuration parameters from pg 42-43 in the ADAU1761 datasheet.

I've taken a look at this tutorial: http://ez.analog.com/message/5675#5675

Jumper configuration for my setup is consistent for clock sync and passing ADC to DAC pins. I've not had any luck setting MCLK to the I2S setting, both boards are set to OSC.

Any ideas?

Best,

John

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  • Welcome to the forums!

    Well, if each board is running off of its own clock source (OSC) then that means the boards are asynchronous by definition. Since neither oscillator is running at exactly the same rate, you will have small drops when a sample is either skipped or doubled by one chip or the other. This is similar to the concept of a beat frequency when two tones are combined. Basically, if one oscillator is running at 12.288000 MHz and the other is running at 12.28800025 MHz (completely possible with the tolerance of some crystals), that means that there is a difference between the two clocks of about 0.25 Hz, meaning that once every 4 seconds, a sample will be missed.

    In order to make both chips synchronized, you really need to have them both running on the same master clock signal.

    You can either take the master clock oscillator signal from one board and run it to the next, or you can take the clock output from one board (a buffered copy of the PLL output) and run that to the next. However, the one thing you can't do is have each chip running off of a separate clock source.

    I hope that helps!

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  • Welcome to the forums!

    Well, if each board is running off of its own clock source (OSC) then that means the boards are asynchronous by definition. Since neither oscillator is running at exactly the same rate, you will have small drops when a sample is either skipped or doubled by one chip or the other. This is similar to the concept of a beat frequency when two tones are combined. Basically, if one oscillator is running at 12.288000 MHz and the other is running at 12.28800025 MHz (completely possible with the tolerance of some crystals), that means that there is a difference between the two clocks of about 0.25 Hz, meaning that once every 4 seconds, a sample will be missed.

    In order to make both chips synchronized, you really need to have them both running on the same master clock signal.

    You can either take the master clock oscillator signal from one board and run it to the next, or you can take the clock output from one board (a buffered copy of the PLL output) and run that to the next. However, the one thing you can't do is have each chip running off of a separate clock source.

    I hope that helps!

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