I've been working with a pair of 1761 eval boards and have run into a mysterious clock sync problem. Every ~4 seconds I have a short amplitude reduction in the output signal. I'm hearing this as a very brief drop out or click in my headphones. Perhaps I've missed a register setting. The audio streams are otherwise working/sounding fine and I'm running them through a pair of the ADI beamforming algorithms.
Passing a digital signal from the slave board to clock master. I've tried Left/Right Justified and TDM modes, following the configuration parameters from pg 42-43 in the ADAU1761 datasheet.
I've taken a look at this tutorial: http://ez.analog.com/message/5675#5675
Jumper configuration for my setup is consistent for clock sync and passing ADC to DAC pins. I've not had any luck setting MCLK to the I2S setting, both boards are set to OSC.