Hello people, I am going to build my own board with the adau1701 so I have been violently reading through the datasheet. The thing is I am a bit confused with PLL settings. In the paragraph "setting maste clock/pll mode" it is written: "If the ADAU1701 is set to receive quad-rate signals (by reducing the number of program steps per sample by a factor of 4 using the core control register), the master clock frequency must be 16 × fS, 64 × fS, 96 × fS, or 128 × fS" But the thing is I use AD adau1701-miniz board for maketing and run a 192khz project, it works fine and yet when I checked the schematic of the board, I found out that the PLL pins on the board were configured to have 256xfS! So I am confused... Does all that mean that if I want to run a 192khz project, I must use a 24mhz resonator and set the PLL pins to 128xfS?? But if so, why the adau1701-miniz board still runs my 192khz project being set up to yield 256xfS?
Guyz, I understand that perhaps this question has been asked with some variations for many times most probably, but I read several topics and still cannot understand. Please help!!
I seem to remember (though I cannot find it now) a post where a designer accidentally overclocked a -1701 by a factor of 2 and that particular chip actually worked that way in the lab. Obviously…
Now I understand. Thank you Bob so much again!! What struck me immediately, is a consequent apparent possibility of "overclocking" the chip somehow. Am I right? I mean, theoretically?