a dummy question about pll in 1701

Hello people, I am going to build my own board with the adau1701 so I have been violently reading through the datasheet. The thing is I am a bit confused with PLL settings. In the paragraph "setting maste clock/pll mode" it is written: "If the ADAU1701 is set to receive quad-rate signals (by reducing the number of program steps per sample by a factor of 4 using the core control register), the master clock frequency must be 16 × fS, 64 × fS, 96 × fS, or 128 × fS"  But the thing is I use AD adau1701-miniz board for maketing and run a 192khz project, it works fine and yet when I checked the schematic of the board, I found out that the PLL pins on the board were configured to have 256xfS! So I am confused... Does all that mean that if I want to run a 192khz project, I must use a 24mhz resonator and set the PLL pins to 128xfS?? But if so, why the adau1701-miniz board still runs my 192khz project being set up to yield 256xfS?

Guyz, I understand that perhaps this question has been asked with some variations for many times most probably, but I read several topics and still cannot understand. Please help!!


  •      Hello Skfir,

         As my friend Mike says, there's no dumb questions (sometimes there's dumb answers, and I hope this isn't one of them).

         The 1701 's fundamental clock is the MIPS clock, which always operates at 49.152 MHz (roughly 50 MIPS) for any "standard" sample rate (48 / 96 / 192 KHz).  The only exception is 44.1 KHz and its multiples, in that case the chip runs about 8% slower, at 45.1584 MIPS.  You're running a standard sample rate (192 KHz), so your -1701 operates at 49.152 MHz.

         As you know, the base 48K sample rate allows for 1024 instructions.  48000 times 1024 equals -- guess what, the 49.152 MIPS rate.  Switching to  192 KHz allows for only 256 instructions, because 256 x 192000 still equals 49.152 MHz.  The chip doesn't run any faster, so you must trade off some program capacity for sample rate.  You set the tradeoff in SigmaStudio's hardware config screen, which in turn sets the core control register in the -1701.  No hardware pins change at all.  That's why your eval board, with its 12.288 MHz crystal, PLLMODE0 = gnd and PLLMODE1=3.3V, can run at any of the standard sample rates.

         What the PLLMODE0 and PLLMODE1 pins allow for is the use of different external clock frequencies if desired.  This directly sets the PLL multiplier, so the MIPS clock remains at roughly 50 MIPS with the different MCLK inputs.  Figure 12 on page 18 of the ADAU1701 data sheet would be a bit less confusing if set up as below:

    Note that earlier on Page 18, ADI recommends that when using the crystal oscillator, you always  use a 12.288 MHz crystal for standard rates (or 11.2896 MHz for 44.1 KHz rate).  To get your ~50 MIPS clock, you set  PLLMODE0 to 0 & PLLMODE1 to 1 which runs the PLL at MCLK x 4. (or 256 x 48000).  Thus, when using the internal crystal oscillator, there's no need to deviate from what's on the evaluation board -- whether your sample rate is 48, 96, or 192 KHz.

         Best regards,

         Bob

  • Now I understand. Thank you Bob so much again!! What struck me immediately, is a consequent apparent possibility of "overclocking" the chip somehow. Am I right? I mean, theoretically?

  •      Hi Skfir,

         I seem to remember (though I cannot find it now) a post where a designer accidentally overclocked a -1701 by a factor of 2 and that particular chip actually worked that way in the lab.   Obviously not recommended, but it does show how robust it is!

         Bob

  • Ha-ha!! Yeah, great. Thanks Bob. Just some 6th sense tells me for some reason that the function of heat dissipation vs frequency increase will be far from linear. Perhaps I am wrong, but in any way it is very interesting!!

  • Hi Bob,

    Thanks! This is FAQ-worthy. I'll convert it to an FAQ now.

    Brett