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ADAU1461 Obsolete
The ADAU1461 is a low power, stereo audio codec with integrated digital audio processing that supports stereo 48 kHz record and playback at 35 mW from...
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ADAU1461 on Analog.com

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ADAU1461 TDM problem

		
	
				

			

									
					    Brettcoupe
					
							

            
            			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Oct 21, 2013 
				
			
			
		
    
		
		                     
				
        		
    
		    
		    		    
		    			
    
			    
    Hi. I have a custom prototype PCB with ADAU1461. Running in slave 8ch TDM
    
 
    However I cannout get an output on the TDM SDO pin. Its always HIGH for bits 32-8 and LOW for 7-0 in the TDM slot.
    
 
    See attached  DSP.JPG
    
 
    my MCLK is 12.288mhz So I am using the PLL x4.
    
 
    My Project even has a Fixed DC signal on one of the TDM slots  to see if the Problem is receiving or sending. and yet still no output.
    
 
    Project attached.
    
 
    Also attached is a DUMP of the Config registers unless I am missing something and surely I must be, They look ok to me.
    
 
    I could really do with some help on this. I have run out of Ideas.
    
 
    Thanks
    
 
    Brett
    
			
    
			
									
		                             
                        

    
    
                                            
                 ADAU1461
                
                                                    
                 Audio Signal Processors
                
                                                    
                 SigmaDSP Audio Processors
                
                                
            
    
    
    
		
    

				
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                on Nov 5, 2013 3:10 PM
            
            
						
			            		
        
		
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        Hi Brett.
        
 
        thankfully I have an FPGA between the TDM master and the ADAU1461 SO I will have to Re format the data there. As the rest of my systen needs delay by 0  32 bit PCM data.
        
 
        I think there is a BUG is Sigma Studio  because all the TDM channel Numbers do not map as Per Fig 62 in the datasheet. Instead of Slots 0-7 being DIG0-7 in SS It appears to be DIG0 is Slot 0 (ie first ) and DIG1 is Slot 4
        
 
        If you simply create a tone signal source and map it to DIG1 output you will see what I mean.
        
 
        Thanks
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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                on Nov 5, 2013 3:10 PM
            
            
						
			            		
          
		
										0
					
	
          

		
		
          
		
          
                                
                                                            
          
					
          Hi Brett.
          
 
          thankfully I have an FPGA between the TDM master and the ADAU1461 SO I will have to Re format the data there. As the rest of my systen needs delay by 0  32 bit PCM data.
          
 
          I think there is a BUG is Sigma Studio  because all the TDM channel Numbers do not map as Per Fig 62 in the datasheet. Instead of Slots 0-7 being DIG0-7 in SS It appears to be DIG0 is Slot 0 (ie first ) and DIG1 is Slot 4
          
 
          If you simply create a tone signal source and map it to DIG1 output you will see what I mean.
          
 
          Thanks
          
			
          

		
			
	      

		
		
	
          
	
          
		
          
			
		
          
	
          
	
          
		
						
						
				
						
				
				
		
		
          
			
		
          
	
          

          

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