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ADAU1461 TDM problem

Hi. I have a custom prototype PCB with ADAU1461. Running in slave 8ch TDM

However I cannout get an output on the TDM SDO pin. Its always HIGH for bits 32-8 and LOW for 7-0 in the TDM slot.

See attached  DSP.JPG

my MCLK is 12.288mhz So I am using the PLL x4.

My Project even has a Fixed DC signal on one of the TDM slots  to see if the Problem is receiving or sending. and yet still no output.

Project attached.

Also attached is a DUMP of the Config registers unless I am missing something and surely I must be, They look ok to me.

I could really do with some help on this. I have run out of Ideas.

Thanks

Brett

attachments.zip
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  • Are you able to change your data source so that there is a one bit delay between the edge of LRCLK and the start of the data? According to Figure 61 in the datasheet, it looks like a one bit delay might be necessary.

    I tried duplicating your setup in the lab with an Audio Precision generating the serial data stream and clocks. It looks like TDM8 mode will work with a 1 bit delay, but it stops working when the data is left-justified (no delay). The easiest solution to the problem is to change the data source so there is a 1 bit delay, if possible.

    If this isn't possible in your system, we might be able to add a capacitor on one of the signal lines to create an artificial delay in the signal and solve the problem that way.

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  • Are you able to change your data source so that there is a one bit delay between the edge of LRCLK and the start of the data? According to Figure 61 in the datasheet, it looks like a one bit delay might be necessary.

    I tried duplicating your setup in the lab with an Audio Precision generating the serial data stream and clocks. It looks like TDM8 mode will work with a 1 bit delay, but it stops working when the data is left-justified (no delay). The easiest solution to the problem is to change the data source so there is a 1 bit delay, if possible.

    If this isn't possible in your system, we might be able to add a capacitor on one of the signal lines to create an artificial delay in the signal and solve the problem that way.

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