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ADAU1461 Obsolete
The ADAU1461 is a low power, stereo audio codec with integrated digital audio processing that supports stereo 48 kHz record and playback at 35 mW from...
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ADAU1461 on Analog.com

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ADAU1461 TDM problem

		
	
				

			

									
					    Brettcoupe
					
							

            
            			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Oct 21, 2013 
				
			
			
		
    
		
		                     
				
        		
    
		    
		    		    
		    			
    
			    
    Hi. I have a custom prototype PCB with ADAU1461. Running in slave 8ch TDM
    
 
    However I cannout get an output on the TDM SDO pin. Its always HIGH for bits 32-8 and LOW for 7-0 in the TDM slot.
    
 
    See attached  DSP.JPG
    
 
    my MCLK is 12.288mhz So I am using the PLL x4.
    
 
    My Project even has a Fixed DC signal on one of the TDM slots  to see if the Problem is receiving or sending. and yet still no output.
    
 
    Project attached.
    
 
    Also attached is a DUMP of the Config registers unless I am missing something and surely I must be, They look ok to me.
    
 
    I could really do with some help on this. I have run out of Ideas.
    
 
    Thanks
    
 
    Brett
    
			
    
			
									
		                             
                        

    
    
                                            
                 ADAU1461
                
                                                    
                 Audio Signal Processors
                
                                                    
                 SigmaDSP Audio Processors
                
                                
            
    
    
    
		
    

				
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                on Nov 1, 2013 1:22 AM
            
            
						
			            		
        
		
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        Hi Brett.
        
 
        If I set the Delay to 0, All that happens is the Entire SDO bit stream shifts One Bit to the Left. Still No MSB.
        
 
        in fact it is impossible to have an MSB in this format as it would be truncated off.
        
 
        The fact that the SDI and SDO Bit patterns MATCH in timing perfectly with "delay by one" is really ODD concidering what your saying that the format of my SDI data is "delay bit by 0".
        
 
        Can you advise if the PROGRAM DATA changes once its loaded into the DSP?
        
 
        If I read back this , Its does not apprear the same as what I put in. All the Configuration data is though.
        
 
        Thanks
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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                on Nov 1, 2013 1:22 AM
            
            
						
			            		
          
		
										0
					
	
          

		
		
          
		
          
                                
                                                            
          
					
          Hi Brett.
          
 
          If I set the Delay to 0, All that happens is the Entire SDO bit stream shifts One Bit to the Left. Still No MSB.
          
 
          in fact it is impossible to have an MSB in this format as it would be truncated off.
          
 
          The fact that the SDI and SDO Bit patterns MATCH in timing perfectly with "delay by one" is really ODD concidering what your saying that the format of my SDI data is "delay bit by 0".
          
 
          Can you advise if the PROGRAM DATA changes once its loaded into the DSP?
          
 
          If I read back this , Its does not apprear the same as what I put in. All the Configuration data is though.
          
 
          Thanks
          
			
          

		
			
	      

		
		
	
          
	
          
		
          
			
		
          
	
          
	
          
		
						
						
				
						
				
				
		
		
          
			
		
          
	
          

          

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