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ADAU1461 Obsolete
The ADAU1461 is a low power, stereo audio codec with integrated digital audio processing that supports stereo 48 kHz record and playback at 35 mW from...
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ADAU1461 on Analog.com

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ADAU1461 TDM problem

		
	
				

			

									
					    Brettcoupe
					
							

            
            			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Oct 21, 2013 
				
			
			
		
    
		
		                     
				
        		
    
		    
		    		    
		    			
    
			    
    Hi. I have a custom prototype PCB with ADAU1461. Running in slave 8ch TDM
    
 
    However I cannout get an output on the TDM SDO pin. Its always HIGH for bits 32-8 and LOW for 7-0 in the TDM slot.
    
 
    See attached  DSP.JPG
    
 
    my MCLK is 12.288mhz So I am using the PLL x4.
    
 
    My Project even has a Fixed DC signal on one of the TDM slots  to see if the Problem is receiving or sending. and yet still no output.
    
 
    Project attached.
    
 
    Also attached is a DUMP of the Config registers unless I am missing something and surely I must be, They look ok to me.
    
 
    I could really do with some help on this. I have run out of Ideas.
    
 
    Thanks
    
 
    Brett
    
			
    
			
									
		                             
                        

    
    
                                            
                 ADAU1461
                
                                                    
                 Audio Signal Processors
                
                                                    
                 SigmaDSP Audio Processors
                
                                
            
    
    
    
		
    

				
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      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Oct 31, 2013 3:51 PM
            
            
						
			            		
      
		
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      It looks like your configuration might not match the data format of your source.
      
 
      Your source (SDI) appears to have left-justified data. In other words, the most significant bit is aligned with the clock edge of the LRCLK signal. This is a delay-by-zero format.
      
 
      You have configured the ADAU1461 for delay-by-one, meaning that it's not expecting the most significant bit until one BCLK cycle after the LRCLK edge.
      
 
      This means that the first data bit will be ignored.
      
 
      To solve the problem, do one of these fixes:
      
 
        
  
      • Change your source format to delay the MSB by one bit... or...
        • 
  
      • Change the configuration in SigmaStudio to delay by one
        • 
 
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
						
				
				
		
		
      
			
		
      
	
      

      

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      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Oct 31, 2013 3:51 PM
            
            
						
			            		
      
		
										0
					
	
      

		
		
      
		
      
                                
                                                            
      
					
      It looks like your configuration might not match the data format of your source.
      
 
      Your source (SDI) appears to have left-justified data. In other words, the most significant bit is aligned with the clock edge of the LRCLK signal. This is a delay-by-zero format.
      
 
      You have configured the ADAU1461 for delay-by-one, meaning that it's not expecting the most significant bit until one BCLK cycle after the LRCLK edge.
      
 
      This means that the first data bit will be ignored.
      
 
      To solve the problem, do one of these fixes:
      
 
        
  
      • Change your source format to delay the MSB by one bit... or...
        • 
  
      • Change the configuration in SigmaStudio to delay by one
        • 
 
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
						
				
				
		
		
      
			
		
      
	
      

      

      • 


    


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