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ADAU1461 Obsolete
The ADAU1461 is a low power, stereo audio codec with integrated digital audio processing that supports stereo 48 kHz record and playback at 35 mW from...
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ADAU1461 on Analog.com

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ADAU1461 TDM problem

		
	
				

			

									
					    Brettcoupe
					
							

            
            			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Oct 21, 2013 
				
			
			
		
    
		
		                     
				
        		
    
		    
		    		    
		    			
    
			    
    Hi. I have a custom prototype PCB with ADAU1461. Running in slave 8ch TDM
    
 
    However I cannout get an output on the TDM SDO pin. Its always HIGH for bits 32-8 and LOW for 7-0 in the TDM slot.
    
 
    See attached  DSP.JPG
    
 
    my MCLK is 12.288mhz So I am using the PLL x4.
    
 
    My Project even has a Fixed DC signal on one of the TDM slots  to see if the Problem is receiving or sending. and yet still no output.
    
 
    Project attached.
    
 
    Also attached is a DUMP of the Config registers unless I am missing something and surely I must be, They look ok to me.
    
 
    I could really do with some help on this. I have run out of Ideas.
    
 
    Thanks
    
 
    Brett
    
			
    
			
									
		                             
                        

    
    
                                            
                 ADAU1461
                
                                                    
                 Audio Signal Processors
                
                                                    
                 SigmaDSP Audio Processors
                
                                
            
    
    
    
		
    

				
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                on Oct 29, 2013 1:48 PM
            
            
						
			            		
        
		
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        Well I finall got the DSP to output some signal.
        
 
         It turns Out the CHIP was defective all this time.
        
 
        I repalced it and YAY some output signal..
        
 
        BUT I do have one last question
        
 
        It appears the DSP is Not passing the First Bit.
        
 
        My Project has Nothing But ALL TDM inputs routed to ALL TDM Outputs in the DSP Schematic.
        
 
        See the Attached Screen Grab of the Logic Analyser
        
 
        Details
        
 
        MCLK  12.288M
        
 
        8ch TDM
        
 
        PLL at 4x
        
 
        SigmaStudio is set to 
        
 
        TDM8 Slave 50%
        
 
         LRCK Falling
        
 
        BLCK Falling
        
 
        BitCLK cycles 256 per frame
        
 
        Data Delay LREdge =1
        
 
        REG 0x4015  = 0x04
        
 
        REG 0x4016 = 0x80
        
 
        is this correct for my incomming TDM Data?
        
 
        Thanks
        
			
        

		
			
	      

				
        
			
			
		
        
			
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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                on Oct 29, 2013 1:48 PM
            
            
						
			            		
          
		
										0
					
	
          

		
		
          
		
          
                                
                                                            
          
					
          Well I finall got the DSP to output some signal.
          
 
           It turns Out the CHIP was defective all this time.
          
 
          I repalced it and YAY some output signal..
          
 
          BUT I do have one last question
          
 
          It appears the DSP is Not passing the First Bit.
          
 
          My Project has Nothing But ALL TDM inputs routed to ALL TDM Outputs in the DSP Schematic.
          
 
          See the Attached Screen Grab of the Logic Analyser
          
 
          Details
          
 
          MCLK  12.288M
          
 
          8ch TDM
          
 
          PLL at 4x
          
 
          SigmaStudio is set to 
          
 
          TDM8 Slave 50%
          
 
           LRCK Falling
          
 
          BLCK Falling
          
 
          BitCLK cycles 256 per frame
          
 
          Data Delay LREdge =1
          
 
          REG 0x4015  = 0x04
          
 
          REG 0x4016 = 0x80
          
 
          is this correct for my incomming TDM Data?
          
 
          Thanks
          
			
          

		
			
	      

				
          
			
			
		
          
			
		
	
          
	
          
		
          
			
		
          
	
          
	
          
		
						
						
				
						
				
				
		
		
          
			
		
          
	
          

          

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