ADAU1701 TDM input slave mode

Hello,

I'm coupling two dsp boards. Both equipped with one ADAU1701. The master board is clocking out TDM in master mode, the slave board's DSP should clock-in the TDM data in slave mode. I know for sure that the serial data from the master is OK because on both boards an 8ch DAC with TDM input is converting the TDM data into audio successfully. The boards contain a CPLD as glue logic, so I'm very flexible with respect to clocks and routing.

The boards are in 256*fs mode (PLL_MODE0 = '0', PLL_MODE1 = '1')

MP0 is TDM data in,

MP4 is TDM LRCK = 48 kHz,

MP5 = TDM BCK = 12,288 MHz,

MCLKI = TDM BCK = 12,288 MHz,

all data and clocks come from the master DSP board. I have a sync masterclock (24,576 MHz) that is fed to the 8ch TDM DACs available from the master DSP board as well.

The DSP on the slave board is not syncing. Do I need to configure something to get it listening to the LRCLKi (MP4) and BCLKi (MP5)? I can't find a "slave" button for the TDM input in the SigmaStudio software. I've included a (not-working) screendump of my config.

Kind regards,

Stefan

  • The serial inputs do not have a master mode checkbox because they are actually only capable of operating as slaves. Your register settings look OK to me, but the bit clock might be inverted. It might be a good idea to invert the bit clock polarity setting or to configure your CPLD to invert that signal.

    Could you please also post a screenshot of the input cell in your project? I just want to make sure you're using the proper input channels.

    See here for a reference: https://wiki.analog.com/resources/tools-software/sigmastudio/toolbox/io/input#adau1701_serial_input_port_routing

  • Dear Brett,

    Thanks for your quick reply. I've been playing with the BCK polarity but that does not get audio on the outputs. I've included the test schematic I'm using. I monitor all inputs with an RTA just in case audio pops up on the wrong channel. I'm listening to channel DAC0 with a small active loudspeaker. The internal analog output channels are quite noisy. The noise on this channel changes a lot when I change BCK settings.

    Are you sure the TDM input is always in slave mode and using MP4 and MP5 for clocking LRCK and BCK by default? I found that the internal analog outputs are very noisy if I do supply LRCK and BCK when I use the DSP in master mode without an external DAC's. Removing these clock signals (in the CPLD) from these pins improves SNR a lot.

  • Hi,

    I've just found out that the MP0 input has to be configured as "Input Sdata_in0" and not as "In TDM 8 ch" just as MP6 for the output. Don't know why the "In TDM 8 ch" and "Out TDM 8 ch" options are available. I don't need them for the TDM mode at all!


  • Thanks for your efforts Brett! Good idea as well to check the config registers with help of the the capture window display, I'll sure be using that in future!

    Kind regards,

    Stefan

  • Thanks for reporting this Stefan. I was really out of ideas!

    I didn't understand why "Input Sdata_in0" seems to be the proper option, and "In TDM 8ch" did not work. So, I compared the software GUI to the datasheet.

    When I try to set the mode of MP0 to "In TDM 8ch", the capture window displays this information:

    Block Write

    Time:  10:13:50 - 792ms

    IC:  IC 1

    Param Name:  IC 1.MpCfg0

    Param Address:  0x0820

    Bytes:  3

    Param Data:

    b00000000 00000000 00000101

    Note that the 4 LSBs are set to 0b0101.

    Now, checking the datasheet, I looked for the corresponding mode for 0b0101. In the screenshot below, you can see that this setting is listed as "Reserved".

    So, this is a bug with the drop-down menu in SigmaStudio. Perhaps "In TDM 8ch" is some outdated test mode for the GPIO pins that was removed in the release version of the chip. I will inform the software team.