We're developing an audio mixer around a ring of ADAU1701s where each receives a TDM steam from its neighbor, adds in two analog inputs and sends the mix through to the next -1701. The block diagram below shows four -1701s, we plan to use six to accommodate all the needed inputs. One of them ("DSP 3") is programmed differently to break this ring -- handling the first inputs while converting the mixed outputs to analog. We're using TDM because several streams are needed for mix-minus, a headphone bus, etc. The -1701s would also perform some audio processing such as EQ, all booted and directed by a PIC microcontroller via two I2C buses.
This is where it gets confusing. I'm assuming first of all that all the TDM outputs would be set up as masters, all inputs would be slaves, and the each output's clocks would feed the next input (as shown above) except of course for MCLK which is synchronous to all. Mike who is designing the unit and who is more comfortable in the "digital snake pit" than myself, would like to see all the clocks synchronous as shown below -- as this would mitigate any accumulated timing errors:
I have no idea if either or both setups would work, or could there be an entirely different way to approach this design. Any suggestions would be appreciated. We're using multiple -1701s because one of these performed so well in our first product, and we like having the analog I/Os built in.
According to my background experience, both of these setups would work. I don't see any real advantage or disadvantage to either approach, other than the following: in the situation where all clocks are synchronous (option 2), you need to make sure the hardware is designed such that there is enough drive strength on the LRCLK/BCLK signal sources to drive 4 slave ICs. That might require extra hardware in the form of clock buffers to deal with the fanout.
Option 1 has the advantage that each ADAU1701 is perfectly capable of driving one slave device from its master I2S port. No problem!
Also, remember that when you approach the problem from the point of view of latency, this is an unavoidable issue: the serial ports and DSP of every device will have latency, regardless of whether that device is a master or a slave. By daisy chaining multiple devices in a serial fashion, latency will accumulate. That is unavoidable. Neither Option 1 nor Option 2 will mitigate this problem. You'll probably want to include delay cells in the SigmaDSP code to appropriately delay the analog signals received in DSPs 2, 3, and 4 to properly align them with the analog signals received by DSP 1.
So, now that I have talked this through, I think I actually prefer option 1 because it potentially simplifies the hardware by avoiding the need for additional buffers.
I would be happy to continue this discussion. Please post any follow-up questions if you have any.
Thank you for your thoughtful answer and your invitation to post additional questions -- which we'll do as they come up while this project advances.
Our prototype has one of the 1701's feeding buttered LRCLK and BCLK to all the others (the second option above). The TDM bus is working well, with the various signals entering and exiting where needed much like cars on the Capitol Beltway. When my friend Mike lays out a board, it's art.
Can I run 2 ADUA1701 in parallel as shown in the link independent of each other for a left and right Channel ? I intend to use the four pots using the 4 ADC for Frequency, Q, Gain, and a line trim for each channel ..
will there be any delay between channels 1 and 2 ?
circuit link on page 50
Thanks in advance
The ADAU1701's analog-in to analog-out delay (latency) is about 1 mS at 48 KHz sample rate. Because this is primarily from the oversampled digital filters within the ADC and DAC, it should match between chips.