I thought I understood the Q number code system but I did the following test
Using 2 DC generators with 0.1 and 0.01 outputs in 5.23 format and the division block the read back output is 1.6?
Can anyone shed any light on this?
1/0.7 = 1.41 and 1/0.07 = 14.1 so some of the numbers work as they should.
That's quite an interesting find you made. Apparently the Sigma 100 (ADAU170x, etc) divide block works by something like the Newton-Raphson method (see http://en.wikipedia.org/wiki/Division_algorithm) -- which first finds the reciprocal of the divisor, then multiplies by the dividend. Thus when the divisor is smaller than (1/15.99 = 0.0625), this intermediate result saturates at 15.99... and the final output becomes 15.99 multiplied by the dividend -- in your case, 15.99 x 0.1 = 1.599. This effect is demonstrated in the circuit below, where the standard divide algorithm and an explicit reciprocal method gives identical results.
Inside some algorithms such as filters, multiplication products exceeding 16 are allowed by a double-precision multiply -- for some reason the -1701 divide algorithm does not (or cannot) take advantage of this.
Finding the reciprocal requires several iterations, which is why the division block uses many instructions -- but it gives you the quotient within the same sample interval. If you need a divide algorithm for slow-moving signals such as envelopes within a compressor side chain, you could try an implicit divide as shown above. It uses a feedback method, reducing the error over many samples. Just like an op-amp circuit, it could go unstable with certain inputs -- if you use it, you'll need to test it with the range of inputs you expect in your application. Or you could scale your inputs to the present divide block to avoid divisors smaller than 0.0625.
Finally, the new Sigma 300 (ADAU145x) processor has built-in log and exponent functions, thus it can perform "true" division with fewer instructions.
Its not been a good day! I started off using the peak compressor module in my project but it has a mute function that cuts the amplification for very low input signals that is not mentioned in the documentation. I also need a real time indication of compression that I was getting by using a stereo compressor and putting a 5:23 format "1" through the compressor to see what it was doing. I then discovered that if you change the delay value to anything but '0', the compressor does not recover but stays at the last amplitude!
After much testing I decided the Peak Compressor module it was not good enough. I then started making a compressor from component parts and hit on this jem with the division. It looks like a scaling problem - I will need to make sure the numbers for the division do not amplify errors in the way the division is implemented and then scale the result after the division is completed.
Thanks for your help with this - I would have got there eventually but you hit the nail on the head. I think I will go home and try again tomorrow.
I hope your design has worked out to your satisfaction.
Recently the ADI programmers came up with a log lookup table for the ADAU1701. In effect this exposes the -1701's log function (which was always inside) to us users. In turn, this made me think if it were possible to perform real-time division via subtracting logs of inputs, as shown below. Unfortunately the tables' linear interpolation, while fine for level meters and such, is not up to the
mathematical precision this task requires. I got only approximate answers. The main reason for my posting this is to save someone else from wasting time on trying it.