ADAU1452 Throughput Delay

Greetings,

I'm hoping to find some information on the expected delay from an I2S Input to output of the ADAU1452 Sigma DSP configured for:

MCLK = 24.576MHz,

PLL divider settings to produce a 294.912MHz system clock,

Audio Fs = 96kHz, BCK = 3.072MHz, I2S (2-ch) format.

no sample rate conversions,

Input and output ports slaved from the same clock signals,

No audio processing, just input straight to output

...So, basically just the minimum 'baseline' latency through the serial input port, dsp core, and output port.  Some colleagues in the lab have measured something longer than expected, and since the datasheet is quiet on the subject, we're unsure if its behaving as expected or not. 

As a corollary, could the latency vary between different input and output ports, or (assuming synchronous clocks), or are the data paths guaranteed synchronous as well (processing notwithstanding)? 

Thanks,

Peter

  • Hi Peter,

    The LRCLK or "sample delay/latency" from input to output can vary slightly.  This depends on if the Start Pulse Source (START PULSE SELECTION REGISTER = address 0xF401) is configured to internal Fs SOUTx or SINx.

    If Start Pulse Source = SOUT or SIN, the delay is 6 cycles

    If Start Pulse Source = Internal fs (48/96/192), the delay is 7 cycles

    The 6 to 7 cycle breakdown is as follows:

    1 frame for the time to get all the data in from serial bus

    1 frame for “FS” resync at the output of the serial inputs

    Within the ADAU145x core are 2 frames

         - 1 frame: Resync all inputs (serial, s/pdif, asrcs,…)  to the chosen start pulse

         - 1 frame: Actual DSP program processing frame

    2 frames: Serial output (double buffered within the ports)

    (An extra clock cycle can be added due to on-chip de-jitter circuits between serial port clocks and internal clocks, depending on Start Pulse source)

    -JT