Sync SPDIF Tx rate to SPDIF Rx rate

Hello Philip,

Which processor are you looking at? Both the ADAU1452 and the ADAU1442 is setup to take the data and clocks from the core sampling rate. They are not run through an ASRC on the output side. The ADAU1452 is capable of routing the SPDIF input directly to the SPDIF output port but that includes data. You cannot take the clocks from the input and data from the core.

The ADAU1452 has a much more featured SPDIF implementation. It is possible to translate the SPDIF RX directly into I2S/TDM format and send it to a serial output port. But this does not gain anything for what you are trying to do. If the SPDIF RX goes away then so will the clocks. The other addition that the ADAU1452 can do is the ability to send out the proper data bits. The 1442 will always have the validity bit set so that can be a problem with other receivers.

The SPDIF TX gets its sample rate clocks from the Core Start Pulse Register in the Sigma300 parts. ( ADAU1452 family) You are able to set the core rate to be the SPDIF_RX rate. So when you do that the TX will be the same as the RX rate. I have not experimented with the Sigma200, ADAU1442 to see if this is true with that part but I think it will work and there is a setting for the SPDIF_RX in the start pulse register. 

The issue is that if the SPDIF signal ever goes away, then the core will lose its start pulse and will not execute the program. It is waiting for the start of the next frame which never comes. As soon as the SPDIF_RX signal comes back it will continue running the program from where it left off. This will cause some discontinuities in the audio. This may or may not be an issue with your application but it needs to be understood so that a system controller could mute the audio. 

The other detail is that all the rest of the inputs and outputs of the DSP will have to go through the ASRC to get to and from the core since they are running at a different sample rate. 

Note: I edited this response on Aug 25, 2021 with the updated understanding of the SPDIF clocking. 

 

Dave T

Hi,

sorry for the long delay, the project got put to one side for a while but I now have the prototype board to start work on.

I am using the ADAU1442.

I plan to try the following, the SPDIF TX will run at the core rate as you describe, this will connect to the SPDIF RX of another ADAU1442 (in a seperate box or I would just use I2S) and the RX will be fed through an SRC since I can't lock the cure speeds of the two boxes together.

This has slightly modifed by original plan I may have problems with the ASRC group delay but I shall have to try it and see what happens.

Thanks for the comprehensive analysis and suggestions

regards

PhilipJ

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