External SPI RAM



I am currently looking to build a 4 tap delay with up to 5 seconds of delay. Each tap will have individual filtering and different modulation options.



I see that the ADAU1452 has an external RAM block, and that this can address up to 16mb of external SPI RAM. Are there any plans to allow multiple tap readings from this block? Or could 4 of these blocks be used for 4 separate delays? Also, are there any plans to increase support for this block across other processor families IE the Sharc DSP's? I would really like to use the SIgmaDSP tool, but my application may be outside the scope of it currently.