External SPI RAM



I am currently looking to build a 4 tap delay with up to 5 seconds of delay. Each tap will have individual filtering and different modulation options.



I see that the ADAU1452 has an external RAM block, and that this can address up to 16mb of external SPI RAM. Are there any plans to allow multiple tap readings from this block? Or could 4 of these blocks be used for 4 separate delays? Also, are there any plans to increase support for this block across other processor families IE the Sharc DSP's? I would really like to use the SIgmaDSP tool, but my application may be outside the scope of it currently.

  • Hello Nathan,

    At the present time this block is not 100% functional as I would like to see it. It works for one instance but not multiple instances. So if you grow it or add a second cell it will not compile. It is on the list to update but I am not sure when this might be completed.

    Now, a few things I want to comment on.:

    RAM size, yes, it can address 16Mb of external SPI but you cannot buy serial SPI that large. The 23LC1024 is 1 Mbit and I heard that Ramtron (Cypress) now has a 4Mbit FRAM so this is going to be the limiting factor.

    4Mbit is half of what you need for 5 seconds of delay (mono). You could take advantage of some utilities in the toolbox that will truncate the data to 16 bits and then you can pack and unpack 16 bit data to theoretically get twice the data read or written. So that would get you to stereo and if you cascaded them as one mono delay I think you may be able to get 5 seconds that way. You would have one tap with this trick.

    Then you could lower the sample rate, that would increase the delay time.

    When we get the multiple instances working there will be a limitation with the speed of the master SPI port. It can run up to around 15MHz but then you start running into the read delay for the memory. So it starts getting a bit more tricky when you push the frequency. So at some point a 4 tap delay is possible once the multichannel functionality is added to the SigmaStudio Ext Delay cell.

    Now as far as support across other processor families. The SHARC is supported by others in the company so I am not sure what exists and what does not. I would think this exists already. The SigmaDSP is a different story. This is the only one that has a master port that can access external RAM.

    I hope this all helps.


    Dave T

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  • Dear Dave Thib

    Are there any news on multiple istance of external delay?

    We need to implement delay for more than one channel and the internal memory is already in use. The best solution for us would be to use one 23LC1024 and place four istances of the external delay.

    Best regards